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@AmirhosseinPoolad AmirhosseinPoolad commented Nov 11, 2025

This PR adds the last piece of functionality for modeling 2.5D architectures in upstream VPR: Actually cutting down the wires and connections that cross between the dice.

I had an issue with code duplication and there are still some functions that look very similar but do different things. I tried my best to keep the duplication to the lowest level functions and have more general higher level functions that wrap them but there's still some remaining. If you have an idea to do this in a better way please let me know.

@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels Nov 11, 2025
@AmirhosseinPoolad AmirhosseinPoolad changed the title [WIP] RR Graph - Cut interposer crossing wires RR Graph - Cut interposer crossing wires Nov 12, 2025
@github-actions github-actions bot added the docs Documentation label Nov 12, 2025
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@AlexandreSinger AlexandreSinger left a comment

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Looks good. Some comments.

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@amin1377 amin1377 left a comment

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Thanks, Amir!

RRNodeId src_node = rr_graph.edge_src_node(edge_id);
RRNodeId sink_node = rr_graph.edge_sink_node(edge_id);

// TODO: ignoring ChanZ nodes for now
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Can you elaborate a bit more on why chanz is ignored? My guess is that since this code is focused on the 2.5D architecture, the assumption is that chanz is not stretched across the 2D plane but along the Z-axis, so the interposer line wouldn’t apply to it. If that’s the case, I’d also add an ASSERT_DEBUG here to ensure that x_low == x_high and y_low == y_high.

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@AmirhosseinPoolad AmirhosseinPoolad Nov 15, 2025

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I haven't thought about 3D architectures that also have interposer cut lines so I'm honestly not sure what should happen to edges to connect to/from chanz nodes. I think this needs further discussions about what it even means to have an architecture like this.

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I'd update the comment to say that we don't allow interposers in the Z dimension (z is for die-stacking, and an interposer in a die stacking dimension is not currently manufacturable).

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It's actually a bit more concerning. We could, for example, have an L16 wire that crosses an interposer cut line, gets to a 3D switch block on the other side and connects to a chan z node. The current version of the code does not remove that edge while ideally it should be removed.

I think this should be addressed in a follow up PR.

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@soheilshahrouz soheilshahrouz left a comment

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Thanks Amir!

}
}

void update_interposer_crossing_nodes_in_spatial_lookup_and_rr_graph_storage(const RRGraphView& rr_graph, const DeviceGrid& grid, RRGraphBuilder& rr_graph_builder, const std::vector<std::pair<RRNodeId, int>>& sg_node_indices) {
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the line is too long
the function name is too long

@github-actions github-actions bot added the libarchfpga Library for handling FPGA Architecture descriptions label Nov 17, 2025
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@vaughnbetz vaughnbetz left a comment

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Looks good; some commenting upgrades and a few changes suggested.

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6 participants