SRIP Pull request

SRIP/Codes/Code_Documentation.md

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+# Code Documentation
+
+## Introduction
+
+This document captures the experiment implementation details.
+
+## Code Details 
+
+1. **File name:** simLayout.html     
+   **File description:** Contains the layout of the circuit simulator.  
+
+2. **File name:** layout.css    
+   **File description:** Contains the css of the simulator.
+
+3. **File name:** simulatorOptions.js     
+   **File description:** Contains the jquery to enable the different options contained in the main simulator file.
+
+4. **File name:** circuitCheck.js     
+   **File description:** Contains the functions necessary to check if the circuit made on the simulator is correct and if all the connections and components are correct.
+
+  * **Function name:** circCheck()   
+  	**Function description:** This retreives the circuit data and checks if it is the same as a preset circuit data.
+
+  * **Function name:** isEqual()   
+    **Function description:** This checks if two objects are equal.
+
+5. **File name:** Procedure.html     
+   **File description:** Contains the procedure to run each simualtion.   
+
+6. **File name:** project_doc.html      
+   **File description:** Contains the theory behind the experiment.   
+
+7. **File name:** project_doc_style.html     
+   **File description:** Contains the css for the project_doc.html.

SRIP/Codes/Experiment_Project_Documentation.md

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+# Experiment Project Documentation
+
+## Introduction
+
+This document captures the technical details related to the experiment development.
+
+## Project 
+**Domain name:** Computer Science & Engineering.    
+**Lab name:** Very Large Scale Integration.    
+**Experiment name:** Schematic Design Of Transistor Level XOR and XNOR gate.    
+
+Pass transistor logic (PTL) describes several logic families used in the design of integrated circuits. It reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Transistors are used as switches to pass logic levels between nodes of a circuit, instead of as switches connected directly to supply voltages.   
+
+This reduces the number of active devices, but has the disadvantage that the difference of the voltage between high and low logic levels decreases at each stage. Each transistor in series is less saturated at its output than at its input.   
+
+This experiment is used to simulate the working of an XOR and XNOR gate using pass transistor logic. A graph is generated which shows the output of the simulation.
+
+## Purpose of the Project
+
+The purpose of this project is to convert XOR and XNOR gate simulation from Java to Javascript.       
+
+## Project Developers Details
+
+| Sl.no |        Name       | Year Of Study |    Role   |           Email-ID          | Github handle |
+|:-----:|:-----------------:|:-------------:|:---------:|:---------------------------:|:-------------:|
+| 1     | Utkarsh Chhapekar | 2nd year      | Developer | utkarshchhapekar2@gmail.com | Utkichaps     |
+
+## Technologies and Libraries
+
+**Technologies:** 
+1. HTML  
+2. CSS  
+3. Javascript  
+
+**Libraries:**  
+1. SimCir JS    
+2. JQuery  
+3. Bootstrap   
+
+## Development Environment
+
+**OS:** Ubuntu 19.04
+
+## Documents and Files:
+
+| Sl.no |      Document      |                                      Role                                      |
+|:-----:|:------------------:|:------------------------------------------------------------------------------:|
+| 1.    | Procedure          | This document captures the instructions to run the simulations                 |
+| 2.    | Test Cases         | This document captures the functional test cases of the  experiment simulation |
+| 3.    | Code Documentation | This document captures the details related to code                             |
+| Sl.no |        File        |                                      Role                                      |
+| 1.    | Codes              | Contains the major code as well as the images related to it.                   |
+| 2.    | Libraries          | Contains libraries used by the code                                            |
+
+## Process Followed to convert the experiment 
+
+1. Understand the assigned experiment Java simulation.
+2. Understanding the experiment concept.
+3. Re-implement the same in javascript.
+
+## Value Added by our Project   
+
+It is beneficial to engineering students who want to understand how pass transistor logic can be used to simulate universal gates and to understand the theory behind it as well.
+
+## Risks and Challenges
+
+A few challenges faced during the development process was understanding the simcir library so that it can be used to retrieve the circuit data dynamically. Adding components was also an issue.
+
+## Issues
+
+No current issues open.

SRIP/Codes/Experiment_Test_Cases_Documentation.md

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+# Experiment Test Cases Documentation
+
+## Introduction
+
+This document captures the test cases of the experiment.
+
+## Functional Test Cases
+
+| Test Case id |                             Test Scenario                            |                                       Test Steps                                       |                              Expected Output                             |                               Actual Output                              | Result |
+|:------------:|:--------------------------------------------------------------------:|:--------------------------------------------------------------------------------------:|:------------------------------------------------------------------------:|:------------------------------------------------------------------------:|:------:|
+| 1.           | Press Simulate button without selecting what type of simulation      | Directly click on simulate without selecting the type of simulation.                   | Alert: Please select type of simulation                                  | Alert: Please select type of simulation                                  | pass   |
+| 2.           | Press Simulate button with mismatched circuit and simulation option. | Choose a simulation and make a circuit which is not the same as the simulation option. | Alert: This is not the correct circuit. Please refer procedure carefully | Alert: This is not the correct circuit. Please refer procedure carefully | pass   |
+| 3.           | Alert when the connections/components are wrong.                     | Make an incorrect circuit and try to simulate it.                                      | Alert: This is not the correct circuit. Please refer procedure carefully | Alert: This is not the correct circuit. Please refer procedure carefully | pass   |
+| 4.           | Graph should get cleared after simulating a wrong circuit.           | Simulate a correct circuit and then simulate a wrong circuit                           | The graph of the previous simulation should not show.                    | The graph of the previous simulation should not show.                    | pass   |    
+
+## Cross Browser Testing
+
+| Sl.no | Browser         | Version       | Works? |
+|-------|-----------------|---------------|--------|
+| 1.    | Google Chrome   | 75.0.3770.100 | Yes    |
+| 2.    | Mozilla Firefox | 67.0.4        | yes    |
+

SRIP/Codes/Procedure.html

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+<!DOCTYPE html>
+<html>
+<head>
+	<title>Procedure</title>
+	<script type="text/javascript" src="../Libraries/jquery-3.4.1.min.js"></script>
+	<style type="text/css">
+		select {
+				  transition-duration: 0.4s;
+				  cursor: pointer;
+				  background-color: white;
+				  color: black;
+				}
+		 select:hover {
+				    background-color: lightgrey;
+				}
+	</style>
+</head>
+<body>
+	<div style="text-align: center;">
+	<h1>Procedure</h1>
+	<select id="choice">
+		<option value="0" selected disabled hidden>Select the circuit</option>
+        <option value="1">XOR gate circuit</option>
+        <option value="2">XNOR gate circuit</option>
+	</select>
+	</div>
+	<div id="pos">
+		<img width="375" src="Images/label.png">
+		<p><strong>Components which will be used for this:</strong>PMOS, NMOS, Input, Output, Vdd, GND, Capacitor, Joint, OJoint.</p><br>
+		<strong>Steps (Can also refer to the diagram below):</strong>
+		<img src="Images/xor.png"><br>
+		<ol>
+			<li>Select <i>XOR Gate</i> from the option on the top of the page, under the heading.</li>
+			<li>Connect two pairs of PMOS (4 in total) in parallel and connect that in series between Vdd and 3 input OR. To do that:</li>
+			<ul>
+				<li>Place two PMOS side by side</li>
+				<li>Connect drain of first PMOS to output of a Joint and connect that to the drain of the second PMOS.</li>
+				<li>Connect Vdd to the input to the input of the above mentioned Joint.</li>
+				<li>Connect source of first PMOS to an OJoint and connect that to source of second PMOS.</li>
+				<br>
+				<li>Place two more PMOS side by side below the above connections.</li>
+				<li>Connect drain of first PMOS to output of a Joint and connect that to the drain of the second PMOS.</li>
+				<li>Connect the input of the above mentioned Joint to the OJoint of the first parallel connection of PMOS.</li>
+				<li>Connect source of first PMOS to an OJoint and connect that to source of second PMOS.</li>
+				<li>Connect the above mentioned OJoint to the first input of the 3 input OR gate.</li>
+			</ul>
+			<li>Connect two pairs of NMOS (4 in total) in series and connect that in parallel between 3 input OR and GND. To do that:</li>
+			<ul>
+				<li>Place four NMOS in the same way the PMOS has been placed.</li>
+				<li>Connect the second input of the 3 input OR gate to an OJoint.</li>
+				<li>Connect the above OJoint to the Drain of the top two NMOS.</li>
+				<li>Connect the source of one of the NMOS to an OJoint and connect that to the Drain of the NMOS below it.</li>
+				<li>Do the above step for the two NMOS on the other side.</li>
+				<li>Connect the source of the bottom two NMOS to the Output of a Joint.</li>
+				<li>Connect the input of the above mentioned Joint to GND.</li>
+			</ul>
+			<li>Connect the GND to the Input of a capacitor.</li>
+			<li>Connect the output of the capacitor to the third input of the 3 input OR.</li>
+			<li>Connect the output of the 3 input OR to an <i>Out</i> component.</li>
+			<li>For the inputs, put 4 <i>In</i> components on the workspace.</li>
+			<li>Each <i>In</i> component should be connected to one PMOS and one NMOS. For this, follow the diagram given above.</li>
+		</ol>
+	</div>
+	<div id="neg">
+		<img width="375" src="Images/label.png">
+		<p><strong>Components which will be used for this:</strong>PMOS, NMOS, Input, Output, Vdd, GND, Capacitor, Joint, OJoint.</p><br>
+		<strong>Steps (Can also refer to the diagram below):</strong>
+		<img src="Images/xnor.png"><br>
+		<ol>
+			<li>Select <i>XOR Gate</i> from the option on the top of the page, under the heading.</li>
+			<li>Connect two pairs of PMOS (4 in total) in parallel and connect that in series between Vdd and 3 input OR. To do that:</li>
+			<ul>
+				<li>Place two PMOS side by side</li>
+				<li>Connect drain of first PMOS to output of a Joint and connect that to the drain of the second PMOS.</li>
+				<li>Connect Vdd to the input to the input of the above mentioned Joint.</li>
+				<li>Connect source of first PMOS to an OJoint and connect that to source of second PMOS.</li>
+				<br>
+				<li>Place two more PMOS side by side below the above connections.</li>
+				<li>Connect drain of first PMOS to output of a Joint and connect that to the drain of the second PMOS.</li>
+				<li>Connect the input of the above mentioned Joint to the OJoint of the first parallel connection of PMOS.</li>
+				<li>Connect source of first PMOS to an OJoint and connect that to source of second PMOS.</li>
+				<li>Connect the above mentioned OJoint to the first input of the 3 input OR gate.</li>
+			</ul>
+			<li>Connect two pairs of NMOS (4 in total) in series and connect that in parallel between 3 input OR and GND. To do that:</li>
+			<ul>
+				<li>Place four NMOS in the same way the PMOS has been placed.</li>
+				<li>Connect the second input of the 3 input OR gate to an OJoint.</li>
+				<li>Connect the above OJoint to the Drain of the top two NMOS.</li>
+				<li>Connect the source of one of the NMOS to an OJoint and connect that to the Drain of the NMOS below it.</li>
+				<li>Do the above step for the two NMOS on the other side.</li>
+				<li>Connect the source of the bottom two NMOS to the Output of a Joint.</li>
+				<li>Connect the input of the above mentioned Joint to GND.</li>
+			</ul>
+			<li>Connect the GND to the Input of a capacitor.</li>
+			<li>Connect the output of the capacitor to the third input of the 3 input OR.</li>
+			<li>Connect the output of the 3 input OR to an <i>Out</i> component.</li>
+			<li>For the inputs, put 4 <i>In</i> components on the workspace.</li>
+			<li>Each <i>In</i> component should be connected to one PMOS and one NMOS. For this, follow the diagram given above.</li>
+		</ol>
+
+	</div>
+
+	<script type="text/javascript">
+		$("#pos").hide();
+		$("#neg").hide();
+		$("#choice").change(function(event)
+		{
+			var ch = document.getElementById("choice").value;
+			if(ch==="1")
+			{
+				$("#pos").show();
+				$("#neg").hide();
+			}
+			else if(ch==="2")
+			{
+				$("#pos").hide();
+				$("#neg").show();
+			}
+		});
+	</script>
+</body>
+</html>

SRIP/Codes/Procedure_Documentation.md

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+# Project Documentation
+
+## Introduction
+
+This document captures the instructions to run the simulation.
+
+## Instructions:
+
+1. Click on the simLayout.html file to see the simulator.
+
+2. Choose what you want to simulate under the _Select the simulation_ heading.
+
+3. Now you can either see the circuit for NAND and NOR under the _See Circuit:_ heading or follow the procedure to design it.
+
+4. Clicking on the procedure tab will open a procedure window on the right. Click on the _Select the circuit_ heading to see the procedure for each circuit.
+
+5. Click on the _Simulator Help_ heading to see instructions on how to use the simulator.
+
+6. Once your circuit is done, click on the _Simulate_ button to observe the graph to the right of the workspace.
+
+7. To read the theory behind the experiment click on the _Project Documentation_ heading.

SRIP/Codes/Readme.txt

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+SRIP
+
+VLSI | issue no 380 | Design Of Transistor Level XOR & XNOR Gate
+
+---------------------------------------------------------------------
+
+Simulator:
+The simulator can be accessed by clicking on the simLayout.html file.
+The Project documentation is in the project_doc.html file.
+
+Files used by the simulator:
+simLayout.html
+Procedure.html
+layout.css
+simulatorOptions.js
+circuitCheck.js
+
+
+