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1. IIR-1st-Order-Stereo-FPGA IIR-1st-Order-Stereo-FPGA Public

   A first-order IIR filter for 16-bit PCM stereo data implemented on an FPGA with fixed-point representation.

   SystemVerilog

2. FIR-Stereo-FPGA FIR-Stereo-FPGA Public

   A FIR filter for 16-bit stereo PCM audio DSP implemented on an FPGA with fixed-point representation.

   SystemVerilog

3. Audio-Gain-Module-FPGA Audio-Gain-Module-FPGA Public

   Reference RTL implementation of a stereo gain stage, showcasing fixed-point DSP decisions and AXI integration on FPGA.

   SystemVerilog

4. Mid-Side-Transform-FPGA Mid-Side-Transform-FPGA Public

   Mid-Side transform RTL (encoder/decoder) in Verilog with AXI-Stream and AXI-Lite control, verified via cycle-accurate simulation on KV260.

   SystemVerilog

5. IIR-Biquad-Stereo-FPGA IIR-Biquad-Stereo-FPGA Public

   Reference RTL implementation of a fixed-point IIR biquad filter with AXI-Stream and AXI-Lite control, validated on FPGA hardware.

   SystemVerilog

6. Non-Linear-Distortion-Module-FPGA Non-Linear-Distortion-Module-FPGA Public

   A deterministic, fixed-latency tanh non-linear distortion DSP block implemented in Verilog and integrated with AXI-Stream, published as a reference RTL design.

   Verilog