Show & Tell: Designing the AsyncBlackboardAdapter — from sync locks to async-native module pipelines #113
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The problem with synchronous adapters
Every Blackboard adapter we've wired so far follows the same sync pattern:
This works fine for a single module. But once we run 29 modules in a CognitiveCycle tick, we have a problem: the slowest adapter determines cycle latency. IIT Φ computation can take 50–500ms for large networks. VLA++ forward passes: 20–80ms. If all 29 adapters run sequentially, we're looking at seconds per cognitive cycle — far from the sub-100ms target for real-time applications.
The async solution (Issue #101)
Issue #101 proposes an AsyncBlackboardAdapter base class. Here's the design we're converging on:
Tick rate heterogeneity
Not all modules should run at the same rate:
bciconsciousnessbio_inspiredknowledge_graphsafetyringsSo the CognitiveCycle needs a multi-rate scheduler, not a single global tick:
Open design questions
Backpressure: if BCI writes at 250 Hz but a subscriber is slower, do we drop stale entries or queue them? Current thinking: keep only the latest entry per type (ring buffer of depth 1 for sensor data).
Safety gating: the Safety adapter needs to run synchronously on every write, not on a timer. Should it be a special
BlackboardMiddlewareclass rather than anAsyncBlackboardAdapter?Error propagation: if IIT Phi raises an exception, should the CognitiveCycle continue without a
consciousness_stateentry, or pause? Current preference: degrade gracefully — missing entries trigger amodule_offlineevent but don't stop the cycle.Testing: how do we write deterministic tests for an async multi-rate scheduler? Proposal: use
asyncio.sleep(0)to yield control in tests + a mock clock viaunittest.mock.patch('asyncio.sleep', ...).What's your take on the multi-rate scheduler approach? Does the
AsyncBlackboardAdapterbase class design look right, or should we go with a different concurrency model (threads? process pool for CPU-heavy modules)?Tracking this in Issue #101.
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