ece1756

fpga labs

at 5133ns FAIL X: 0.140198 Expected Y: 1.150501 Got Y: 1.073489 Error: 0.077013 < 0.045000

at 5277ns FAIL X: 3.374756 Expected Y: 25.526511 Got Y: 6.185497 Error: 19.341015 < 0.045000

at 5421ns FAIL X: 3.054749 Expected Y: 19.315723 Got Y: 5.269158 Error: 14.046565 < 0.045000

at 5565ns FAIL X: 0.445984 Expected Y: 1.562015 Got Y: 1.259827 Error: 0.302188 < 0.045000

at 5709ns FAIL X: 3.698364 Expected Y: 33.527879 Got Y: 7.234717 Error: 26.293162 < 0.045000

at 5853ns FAIL X: 2.359924 Expected Y: 10.237271 Got Y: 3.655158 Error: 6.582113 < 0.045000

at 5997ns FAIL X: 1.651001 Expected Y: 5.175761 Got Y: 2.467050 Error: 2.708711 < 0.045000

at 6141ns FAIL X: 1.010254 Expected Y: 2.744582 Got Y: 1.718111 Error: 1.026470 < 0.045000

at 6285ns FAIL X: 1.281128 Expected Y: 3.593229 Got Y: 2.001583 Error: 1.591646 < 0.045000

at 6429ns FAIL X: 2.267822 Expected Y: 9.385154 Got Y: 3.476481 Error: 5.908673 < 0.045000

at 6573ns FAIL X: 0.239319 Expected Y: 1.270383 Got Y: 1.129773 Error: 0.140610 < 0.045000

at 6717ns FAIL X: 1.531799 Expected Y: 4.603725 Got Y: 2.306508 Error: 2.297217 < 0.045000

at 6861ns FAIL X: 3.903503 Expected Y: 39.659827 Got Y: 7.967499 Error: 31.692328 < 0.045000

at 7005ns FAIL X: 3.112427 Expected Y: 20.324626 Got Y: 5.425785 Error: 14.898841 < 0.045000

at 7149ns FAIL X: 0.248901 Expected Y: 1.282615 Got Y: 1.135415 Error: 0.147200 < 0.045000

at 7293ns FAIL X: 3.393311 Expected Y: 25.935299 Got Y: 6.242246 Error: 19.693053 < 0.045000

at 7437ns FAIL X: 0.620972 Expected Y: 1.860649 Got Y: 1.384706 Error: 0.475943 < 0.045000