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wolfTPM Fixes for buffer checking and zeroization #476

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Merged
aidangarske merged 12 commits into from
Apr 7, 2026
Merged

wolfTPM Fixes for buffer checking and zeroization #476

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98327ea
Fix Fenrir F-1227: MMIO register access for multi-byte read/write
dgarske Apr 6, 2026
e0ba069
Fix Fenrir F-1229: EC_Ephemeral parameter marshaling
dgarske Apr 6, 2026
681e1dd
Fix Fenrir F-1754: wolfTPM2_VerifyHash to check key type before readi…
dgarske Apr 6, 2026
d20af38
Fix Fenrir F-1755/F-1762: wolfTPM2_NVReadAuthPolicy read size check
dgarske Apr 6, 2026
d81d7f5
Fix Fenrir F-2159: wolfTPM2_SetAuthSession nonce handling
dgarske Apr 6, 2026
e6e2304
Fix Fenrir F-1758/F-1759/F-1760: ECDH output cleanup on return
dgarske Apr 6, 2026
44fcd9f
Fix Fenrir F-1761: wolfTPM2_RsaDecrypt output cleanup on all return p…
dgarske Apr 6, 2026
b5f66e9
Fix Fenrir F-1764: wolfTPM2_EncryptDecryptBlock output cleanup
dgarske Apr 6, 2026
37335a8
Fix Fenrir F-2161: Add TPM response size validation in tpm2.c
dgarske Apr 6, 2026
6b59c25
Fix Fenrir F-2165: Add size validation in TPM2_Packet_ParsePublic
dgarske Apr 6, 2026
92854c5
Fix Fenrir F-2166: Add size validation in TPM2_Packet_ParseAttest
dgarske Apr 6, 2026
44788c1
Peer review fixes
dgarske Apr 7, 2026
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19 changes: 16 additions & 3 deletions hal/tpm_io_mmio.c
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Original file line number Diff line number Diff line change
Expand Up @@ -37,8 +37,8 @@
#ifdef WOLFTPM_INCLUDE_IO_FILE
#ifdef WOLFTPM_MMIO

#ifndef MIMO_BASE_ADDRESS
#define MIMO_BASE_ADDRESS 0xFE000000u
#ifndef MMIO_BASE_ADDRESS
#define MMIO_BASE_ADDRESS 0xFE000000u
#endif

#ifndef WOLFTPM_ADV_IO
Expand Down Expand Up @@ -100,20 +100,31 @@ int TPM2_IoCb_Mmio(TPM2_CTX *ctx, int isRead, word32 addr, byte* buf, word16 siz
{
size_t i;
word32 effectiveAddr;
word32 regOffset;
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rizlik marked this conversation as resolved.
int isFifo;

/* Bounds check to prevent address wrap-around */
if (addr >= TPM_MMIO_MAX_OFFSET) {
return TPM_RC_FAILURE;
}

effectiveAddr = MIMO_BASE_ADDRESS + addr;
effectiveAddr = MMIO_BASE_ADDRESS + addr;

/* FIFO registers use the same address for every access
* (hardware auto-increments internally).
* Non-FIFO registers need the address advanced for multi-byte access. */
regOffset = addr & 0x0FFFu;
isFifo = (regOffset == TPM_TIS_DATA_FIFO_OFFSET ||
regOffset == TPM_TIS_XDATA_FIFO_OFFSET);

/* IO for 32-bit aligned */
for (i = 0; ((size_t)size - i) >= sizeof(word32); i += sizeof(word32)) {
if (isRead)
TPM2_Mmio_Read32(effectiveAddr, buf + i);
else
TPM2_Mmio_Write32(effectiveAddr, buf + i);
if (!isFifo)
effectiveAddr += sizeof(word32);
}

/* IO for unaligned remainder */
Expand All @@ -122,6 +133,8 @@ int TPM2_IoCb_Mmio(TPM2_CTX *ctx, int isRead, word32 addr, byte* buf, word16 siz
TPM2_Mmio_Read8(effectiveAddr, buf + i);
else
TPM2_Mmio_Write8(effectiveAddr, buf + i);
if (!isFifo)
effectiveAddr++;
}

(void)ctx;
Expand Down
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