STM32N6 (NUCLEO-N657X0-Q) wolfIP Port#85
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…a path WIP
New bare-metal port for STM32N657X0 Cortex-M55 on NUCLEO-N657X0-Q board.
Working:
- UART at 115200 via USART1 PE5/PE6 (VCP confirmed)
- PLL clock config: 600MHz CPU, PLL1 VCO 1200MHz
- LAN8742A PHY detected at addr 0, link UP 100Mbps FD
- ETH DMA configured with no bus errors (buffers in AXISRAM2)
- wolfIP stack init, TCP echo socket, main loop running
- Flash via OpenOCD flash.sh to AXISRAM1
Not yet working:
- RMII data path: MAC debug register shows idle (0x00), zero frames
received by DMA despite PHY link UP and RJ45 LEDs active.
Likely needs full HAL ETH_MACDMAConfig register set replicated.
Key N6 differences from H5/H7 (discovered during bring-up):
- ETH1 on AHB5 at 0x58036000 (not 0x50028000)
- ETH clocks in RCC_AHB5ENR bits 22-24, use SET register (+0x800)
- RMII mode via RCC_CCIPR2 bit 18 (offset 0x148)
- RMII pins all on GPIOF AF11 (PF4/7/10-15) + PG11 MDC
- VDDIO3 is 1.8V — needs HSLV via BSEC shadow FVR124 bit 15
- AXISRAM2+ powered down by default, needs RAMCFG SRAMSD clear
- RIMC master 6 (ETH1) needs CID=1, SEC, PRIV config
- RCC peripheral enables use SET registers (ENSR at +0x800)
- USART clock is 32MHz at HSI (BRR=278 for 115200)
- HardFault handler must not access unclocked peripherals (LOCKUP)
1. RISAF3 (AXISRAM2 firewall) — default base region ENDR=0xFFF
covered only 4KB. ETH DMA buffers at offset 0xF8000 were
blocked. Extended region to cover full 1MB with all CIDs
read+write, SEC=1 for secure-alias access.
2. RIMC CID mismatch — ETH DMA was configured as CID=0 (default)
but RISAF grants access by CID. Changed to CID=1 matching
the CPU and CubeN6 HAL (RISAF_Config). Also added RISC
slave security attributes for ETH1 peripheral.
3. MACCR SARC=3 was inserting 6 extra bytes (source address)
into TX frames instead of replacing, corrupting the Ethernet
header. Removed SARC — wolfIP constructs complete frames.
- SAU: clear all regions, set ALLNS=1 (matching CubeN6 SystemInit)
- RCC ETH peripheral reset before init for clean state
- eth_start: fix raw cast to use ETH_DMA_ADDR for tail pointer
- eth_poll: restore des0 (buffer address) on descriptor re-arm,
since GMAC v5 writeback overwrites des0 with timestamp
- eth_start: arm RX descriptors after DMA start (HAL flow)
- Enable DMA interrupt flags (DMACIER) for proper operation
- ETH buffers placed at 0x341F8000 (end of AXISRAM2, matching
CubeN6 HAL descriptor placement)
- D-cache re-enabled with MPU non-cacheable region for ETH buffers
- AHBSRAM1/2 clocks enabled for potential future use
Tested: ping (5/5, <0.2ms RTT), TCP echo on port 7.
offset 0x1180 is DMAC1CR on N6 (clobbers CH1 DMA config)
- Add named DMACIER/DMAC1IER defines, replace magic numbers
- Remove unused debug functions (get_rx_des0, get_rx_ring_addr,
get_rx_tail, kick_rx) from driver and header
- Fix stale DMACCR comment (DSL=1 doubleword skip, not DSL=0)
- Make CH1 RX descriptor init consistent with CH0 (arm in eth_start)
- Remove unused defines (GPIOA/B/C, read-only ENR regs, AHB1RSTR)
- Remove AHBSRAM linker region and clock enables (unused)
- Guard boot LED blink behind DEBUG_BLINK
- Fix comments (linker script, LED pin)
- Add CI workflow: compile-check with arm-none-eabi-gcc
- Add README.md for N6 port
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- Restored stm32_eth_get_dmacsr() - Hardware TRNG - SAU comment - cppcheck suppressions
dgarske
requested changes
Mar 24, 2026
danielinux
approved these changes
Mar 25, 2026
dgarske
approved these changes
Mar 25, 2026
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Description
Summary
Test plan
stm32n6-build.ymlpasses (arm-none-eabi-gcc compile check)ping -c 5 192.168.12.115/5 repliesecho test | nc -q1 192.168.12.11 7and echoed back