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Thumb2 inline ASM: IAR doesn't do register variables#6943

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dgarske merged 1 commit intowolfSSL:masterfrom
SparkiDev:iar_inline_asm_no_register
Nov 7, 2023
Merged

Thumb2 inline ASM: IAR doesn't do register variables#6943
dgarske merged 1 commit intowolfSSL:masterfrom
SparkiDev:iar_inline_asm_no_register

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Description

IAR doesn't parse register variable declarations with specified registers. IAR doesn't even honor the register keyword.

Fixes zd#16936

Testing

Tested armv7m build with SP and asm.

Checklist

  • added tests
  • updated/added doxygen
  • updated appropriate READMEs
  • Updated manual and documentation

@SparkiDev SparkiDev self-assigned this Nov 2, 2023
@SparkiDev SparkiDev force-pushed the iar_inline_asm_no_register branch 3 times, most recently from ceaa325 to 7f28df4 Compare November 3, 2023 00:34
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Thanks Sean for looking into this.

For me this builds fine in IAR now with WOLFSSL_SP_NO_UMAAL.

/* Single Precision Math optimizations */
#define WOLFSSL_HAVE_SP_RSA
#define WOLFSSL_HAVE_SP_DH
#define WOLFSSL_HAVE_SP_ECC
#define WOLFSSL_SP_ARM_CORTEX_M
#define WOLFSSL_SP_ARM_CORTEX_M_ASM
#define WOLFSSL_SP_SMALL
#define WOLFSSL_SP_MATH_ALL
#define WOLFSSL_SP_NO_DYN_STACK
#define WOLFSSL_SP_NO_UMAAL

Customer reports same, but the wolfCrypt test fails ECC test and the performance is degraded compared to v5.6.3.

ecc_test_curve_size 32 failed! 
keySize=32, Default 
ECC test failed! 
error L=26347 code=-3 
[fiducial line numbers: 7911 24478 36555 48734]

Only ECC is slower:

v5.6.3:

RSA     2048   public       404 ops took 1.002 sec, avg 2.480 ms, 403.194 ops/sec
RSA     2048  private        12 ops took 1.051 sec, avg 87.583 ms, 11.418 ops/sec
DH      2048  key gen        24 ops took 1.007 sec, avg 41.958 ms, 23.833 ops/sec
DH      2048    agree        24 ops took 1.002 sec, avg 41.750 ms, 23.952 ops/sec
ECC   [      SECP256R1]   256  key gen       534 ops took 1.003 sec, avg 1.878 ms, 532.403 ops/sec
ECDHE [      SECP256R1]   256    agree       278 ops took 1.000 sec, avg 3.597 ms, 278.000 ops/sec
ECDSA [      SECP256R1]   256     sign       364 ops took 1.005 sec, avg 2.761 ms, 362.189 ops/sec
ECDSA [      SECP256R1]   256   verify       184 ops took 1.002 sec, avg 5.446 ms, 183.633 ops/sec

v5.6.4:

RSA     2048   public       504 ops took 1.000 sec, avg 1.984 ms, 504.000 ops/sec
RSA     2048  private        14 ops took 1.035 sec, avg 73.929 ms, 13.527 ops/sec
DH      2048  key gen        30 ops took 1.031 sec, avg 34.367 ms, 29.098 ops/sec
DH      2048    agree        30 ops took 1.031 sec, avg 34.367 ms, 29.098 ops/sec
ECC   [      SECP256R1]   256  key gen       228 ops took 1.003 sec, avg 4.399 ms, 227.318 ops/sec
ECDHE [      SECP256R1]   256    agree       378 ops took 1.004 sec, avg 2.656 ms, 376.494 ops/sec
ECDSA [      SECP256R1]   256     sign       186 ops took 1.007 sec, avg 5.414 ms, 184.707 ops/sec
ECDSA [      SECP256R1]   256   verify       130 ops took 1.003 sec, avg 7.715 ms, 129.611 ops/sec

@SparkiDev SparkiDev force-pushed the iar_inline_asm_no_register branch from 7f28df4 to 0729ae7 Compare November 7, 2023 00:09
IAR doesn't parse register variable declarations with specified
registers. IAR doesn't even honor the register keyword.
Can use small negative but IAR doesn't like it.
Specify the positive value instead.
Add a small code size version of mont_reduce_full using umlal and umaal.
Make 'asm' usage in variables use keyword '__asm__'.
Explicitly don't inline some functions when compiling with IAR.
@SparkiDev SparkiDev force-pushed the iar_inline_asm_no_register branch from 0729ae7 to cefe108 Compare November 7, 2023 06:12
@SparkiDev SparkiDev assigned dgarske and unassigned SparkiDev Nov 7, 2023
@dgarske dgarske merged commit 0fa47e9 into wolfSSL:master Nov 7, 2023
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2 participants