USB1 HS working on STM32H7S78-DK but has race condition

[Sambsc19]

I am working on CDC_ACM sample for STM32H7S78-DK using USB1 HS on zephyr 4.4.0. I am building external flash app with the latest mcuboot using:

west build -p always -b stm32h7s78_dk/stm32h7s7xx/ext_flash_app . --sysbuild -- -DEXTRA_DTC_OVERLAY_FILE="app.overlay"

I have created the PHY and PPC drivers:

• zephyr\drivers\usb\common\stm32\phy_h7rsotghs.c
• zephyr\drivers\usb_c\ppc\st_tcpp0203.c

The PHY and power path work well. My issue seems to be between ucpd_stm32.c and main.c. With logging enabled USB is detected and enumerates. When I disable logging or set default log level 2 the ucpd code breaks. The UPCD "contract" seems to be in order according to the attached figure from an5418-how-to-build-a-simple-usbpd-sink-application-with-stm32cubemx-stmicroelectronics.pdf but no timing requirements are specified.

I have attached the working logs with log default level inf and the broken logs with log default level wrn. I often see RX incomplete error as below so I potentially have an issue with half-bit sampling clock. I believe i used the same config as on the stm32G0 sample.

[00:00:03.545,000] <err> ucpd_stm32: UCPD RX incomplete: byte_count=6 expected=8 header=0x108f; dropping

I have verified HS:

[00:00:03.973,000] <inf> usbd_core: Actual device speed 2

USB1-HS-working-with-logs.txt

USB1-HS-broken-with-log-level-wrn.txt

My working branch is at: https://github.com/Sambsc19/zephyr/tree/260618-usbc-working-backup

I have attached the cdc_acm app below. (\boards\stm32h7s78_dk_stm32h7s7xx_ext_flash_app.overlay is used)

cdc_acm.zip

@FRASTM @josuah @avolmat-st @kartben