RISC-V: architecture lacks cache management implementation

[AFOliveira]

Is your feature request related to a problem? Please describe.

RISC-V architecture in Zephyr does not provide implementations for cache management functions (arch_dcache_, arch_icache_), causing build failures when boards declare cache support via CONFIG_CPU_HAS_ICACHE/CONFIG_CPU_HAS_DCACHE and tests attempt to use cache management APIs.

Describe the solution you'd like

Implement RISC-V cache management functions. RISC-V has standardized cache management through the Zicbom (Cache Block Management Operations) extension, which provides instructions like:

cbo.clean - Clean cache line
cbo.flush - Flush cache line
cbo.inval - Invalidate cache line

The implementation would need to:

Create arch/riscv/core/cache.c (or add inline implementations to headers)
Implement all required arch_cache_ functions
Use Zicbom instructions where available, with appropriate feature detection
Handle cases where Zicbom is not available

Describe alternatives you've considered

No response

[JarmouniA]

Please take a look at https://docs.zephyrproject.org/latest/hardware/cache/config.html

causing build failures when boards declare cache support via CONFIG_CPU_HAS_ICACHE/CONFIG_CPU_HAS_DCACHE and tests attempt to use cache management APIs.

CONFIG_CPU_HAS_ICACHE/CONFIG_CPU_HAS_DCACHE are selected at the CPU core/Arch level
"These options have the goal to document an available hardware feature and should be set whether we plan to support and use the cache control in Zephyr or not."

CONFIG_CACHE_MANAGEMENT is supposed to be enabled by a SoC/SoC Family/Platform to indicate that
"the cache operations are exposed to the user through a standard API"

[AFOliveira]

@JarmouniA Thank you for the clarification and the helpful documentation link!

Although, I was trying to use the cache management API in my RISC-V board defintion, and that's when I discovered that enabling CONFIG_CACHE_MANAGEMENT causes twister failures because the required arch_*cache_* functions aren't implemented for RISC-V yet. That's what prompted me to open this issue. I may have described it in a deviating way.

I understand that cache may still be operating automatically at the hardware level regardless of whether it's declared or managed through software. My issue is specifically about the missing software-level cache management implementation that would allow explicit cache control operations (flush/invalidate/etc.) through Zephyr's cache API on RISC-V platforms. Especially, since RISC-V has standardized extensions for cache management (Zicbom - Cache Block Management Operations). So the architecture does have the necessary hardware support - we just can implement the software layer in Zephyr to expose these capabilities through the standard cache API.

Thus, using this issue as a placeholder for a feature request should be fine right?

[JarmouniA]

I discovered that enabling CONFIG_CACHE_MANAGEMENT causes twister failures

That might be an issue that should be fixed separately from the feature request, which twister tests are failing exactly? (assuming by failing you mean not compiling)
Apps are supposed to use the API in include/zephyr/cache.h which should compile even if the interface is not implemented.

[AFOliveira]

Apps are supposed to use the API in include/zephyr/cache.h which should compile even if the interface is not implemented.

I supposed it was because it was not implemented, but I will take a closer look and update here. Thanks!