Enable DTCM and ITCM of core R8 on Renesas RZ/V2H #100500
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added 3 commits
December 4, 2025 16:00
Add itcm, dtcm and sram3 region for RZ/V2H core CR8 Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com> Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
- Enable the DTCM region in soc.c - Apply MPU configuration for the new memory region (itcm, dtcm, sram,...) - Turn on the Kconfig to relocate the vector table to 0x0. Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com> Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Update the memory layout to use the SRAM3 node for board RZ/V2H core CR8 Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com> Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
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tiennguyenzg
approved these changes
Dec 9, 2025
henrikbrixandersen
approved these changes
Dec 9, 2025
henrikbrixandersen
merged commit 5392683
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zephyrproject-rtos:main
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In the previous implementation, the sram node was treated as a single large RAM block that included ITCM, DTCM, and general SRAM, starting at address 0x0 with a total size of 256 MB.
However, Arm Cortex-R8 MPCore Processor r0p2 Technical Reference Manual, DTCM cannot store executable instructions. If an application grows large enough, the linker may place instructions in the DTCM area, which begins at address 0x20000, leading to invalid execution.
This PR updates the memory layout to use the sram3 node and relocates the vector table into the ITCM region. The entire DTCM region is now left unused by default so that applications may choose how to use it explicitly.
The MPU configuration has also been updated to align with the new memory layout.