drivers: dp: add STM32 support #89207
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Okay did a bit of refactoring, platforms have specific headers now, only one guard in the main file. |
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Move the nrf specific functions to a separate file so that every soc has a dedicated header. Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add support for direct control of STM32 gpios to the DP driver. Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
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Added hsem locking, for multi-core devices, same as |
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| z_stm32_hsem_lock(CFG_HW_GPIO_SEMID, HSEM_LOCK_DEFAULT_RETRY); | ||
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| val = LL_GPIO_ReadOutputPort(gpio); | ||
| val |= BIT(pin); | ||
| LL_GPIO_WriteOutputPort(gpio, val); | ||
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| z_stm32_hsem_unlock(CFG_HW_GPIO_SEMID); |
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Is it significantly faster than just GPIO API? I guess z_stm32_hsem_lock/unlock will be optimized away on single core?
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Yes and yes, I think about 250khz vs 550khz on the C0, something like 800 on the H7 can't remember right now but yeah decent boost, I can take a trace if you want me to. Lock and lock are indeed no-ops on single cores, and those are all fast parts, otherwise it would have killed the poor C0.
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FYI @fabiobaltieri
| val = LL_GPIO_ReadOutputPort(gpio); | ||
| val |= BIT(pin); | ||
| LL_GPIO_WriteOutputPort(gpio, val); |
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LL_GPIO_SetOutputPin is a single write and performs RMW atomically in hardware. Am I missing some context, or couldn't it be used here?
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Oh, brilliant, so no lock needed. Thanks for pointing that out I'll send a followup to use that instead and drop the locks.
| val = LL_GPIO_ReadOutputPort(gpio); | ||
| val &= ~BIT(pin); | ||
| LL_GPIO_WriteOutputPort(gpio, val); |
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Ditto but with LL_GPIO_ResetOutputPin instead.
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Add support for direct control of STM32 gpios to the DP driver.
Tested on an F3 and on an H7, should work on all of them.