Initial Support for ElemRV-N

MAINTAINERS.yml

@@ -126,6 +126,19 @@ ACPI:
   tests:
     - acpi
 
+Aesc Platform:
+  status: maintained
+  maintainers:
+    - dnltz
+  files:
+    - soc/aesc/
+    - dts/riscv/aesc/
+    - boards/aesc/
+  files-regex:
+    - ^drivers/.*aesc(\.c)?$
+  labels:
+    - "area: Aesc Silicon Platform"
+
 Antmicro platforms:
   status: maintained
   maintainers:

boards/aesc/elemrv/Kconfig.elemrv

@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Aesc Silicon
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ELEMRV
+	select SOC_ELEMRV_N

boards/aesc/elemrv/board.yml

@@ -0,0 +1,6 @@
+board:
+  name: elemrv
+  full_name: ElemRV-N
+  vendor: aesc
+  socs:
+  - name: elemrv_n

boards/aesc/elemrv/doc/index.rst

@@ -0,0 +1,72 @@
+.. zephyr:board:: elemrv
+
+Overview
+********
+
+ElemRV-N is an end-to-end open-source RISC-V microcontroller designed using SpinalHDL.
+
+Version 0.2 of ElemRV-N was successfully fabricated using `IHP's Open PDK`_, a 130nm open semiconductor process, with support from `FMD-QNC`_.
+
+For more details, refer to the official `GitHub Project`_.
+
+.. note::
+   The currently supported silicon version is ElemRV-N 0.2.
+
+Supported Features
+******************
+
+.. zephyr:board-supported-hw::
+
+System Clock
+============
+
+The system clock for the RISC-V core is set to 20 MHz. This value is specified in the ``cpu0`` devicetree node using the ``clock-frequency`` property.
+
+CPU
+===
+
+ElemRV-N integrates a VexRiscv RISC-V core featuring a 5-stage pipeline and the following ISA extensions:
+
+* M (Integer Multiply/Divide)
+* C (Compressed Instructions)
+
+It also includes the following general-purpose ``Z`` extensions:
+
+* Zicntr – Base Counter and Timer extensions
+* Zicsr – Control and Status Register operations
+* Zifencei – Instruction-fetch fence
+
+The complete ISA string for this CPU is: ``RV32IMC_Zicntr_Zicsr_Zifencei``
+
+Hart-Level Interrupt Controller (HLIC)
+======================================
+
+Each CPU core is equipped with a Hart-Level Interrupt Controller, configurable through Control and Status Registers (CSRs).
+
+Machine Timer
+=============
+
+A RISC-V compliant machine timer is enabled by default.
+
+Serial
+======
+
+The UART (Universal Asynchronous Receiver-Transmitter) interface is a configurable serial communication peripheral used for transmitting and receiving data.
+
+By default, ``uart0`` operates at a baud rate of ``115200``, which can be adjusted via the elemrv device tree.
+
+To evaluate the UART interface, build and run the following sample:
+
+.. zephyr-app-commands::
+   :board: elemrv/elemrv_n
+   :zephyr-app: samples/hello_world
+   :goals: build
+
+.. _GitHub Project:
+   https://github.com/aesc-silicon/elemrv
+
+.. _IHP's Open PDK:
+   https://github.com/IHP-GmbH/IHP-Open-PDK
+
+.. _FMD-QNC:
+   https://www.elektronikforschung.de/projekte/fmd-qnc

boards/aesc/elemrv/elemrv_elemrv_n.dts

@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2025 Aesc Silicon
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <aesc/elemrv-n.dtsi>
+
+/ {
+	model = "ElemRV-N";
+	compatible = "aesc,elemrv-n";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &hyperbus;
+		zephyr,flash = &flash;
+	};
+
+	soc {
+		ocram: memory@80000000 {
+			device_type = "memory";
+			compatible = "mmio-sram";
+			reg = <0x80000000 DT_SIZE_K(1)>;
+		};
+
+		hyperbus: memory@90000000 {
+			device_type = "memory";
+			compatible = "mmio-sram";
+			reg = <0x90000000 DT_SIZE_K(32)>;
+		};
+
+		flash: flash@a0010000 {
+			compatible = "soc-nv-flash";
+			reg = <0xa0010000 DT_SIZE_K(32)>;
+		};
+	};
+};
+
+&uart0 {
+	clock-frequency = <DT_FREQ_M(20)>;
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&cpu0 {
+	clock-frequency = <DT_FREQ_M(20)>;
+};

boards/aesc/elemrv/elemrv_elemrv_n.yaml

@@ -0,0 +1,9 @@
+identifier: elemrv/elemrv_n
+name: ElemRV-N
+type: mcu
+arch: riscv
+toolchain:
+  - cross-compile
+  - zephyr
+ram: 32
+flash: 32

boards/aesc/elemrv/elemrv_elemrv_n_defconfig

@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Aesc Silicon
+# SPDX-License-Identifier: Apache-2.0
+
+# Serial Driver
+CONFIG_SERIAL=y
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y

boards/aesc/index.rst

@@ -0,0 +1,10 @@
+.. _boards-aesc:
+
+Aesc Silicon
+############
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*

doc/releases/release-notes-4.2.rst

@@ -247,6 +247,10 @@ New Boards
 
    * :zephyr:board:`versalnet_rpu` (``versalnet_rpu``)
 
+* Aesc Silicon
+
+   * :zephyr:board:`elemrv` (``elemrv``)
+
 * aithinker
 
    * :zephyr:board:`ai_wb2_12f` (``ai_wb2_12f``)

drivers/serial/CMakeLists.txt

@@ -17,6 +17,7 @@ zephyr_library_sources_ifdef(CONFIG_USB_CDC_ACM ${ZEPHYR_BASE}/misc/empty_file.c
 zephyr_library_sources_ifdef(CONFIG_LEUART_GECKO leuart_gecko.c)
 zephyr_library_sources_ifdef(CONFIG_LPUART_ESP32 lpuart_esp32.c)
 zephyr_library_sources_ifdef(CONFIG_SERIAL_ESP32_USB serial_esp32_usb.c)
+zephyr_library_sources_ifdef(CONFIG_UART_AESC uart_aesc.c)
 zephyr_library_sources_ifdef(CONFIG_UART_ALTERA uart_altera.c)
 zephyr_library_sources_ifdef(CONFIG_UART_ALTERA_JTAG uart_altera_jtag.c)
 zephyr_library_sources_ifdef(CONFIG_UART_APBUART uart_apbuart.c)

drivers/serial/Kconfig

@@ -157,6 +157,7 @@ config UART_SHELL
 comment "Serial Drivers"
 
 # zephyr-keep-sorted-start
+rsource "Kconfig.aesc"
 rsource "Kconfig.altera"
 rsource "Kconfig.altera_jtag"
 rsource "Kconfig.apbuart"

drivers/serial/Kconfig.aesc

@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Aesc Silicon
+# SPDX-License-Identifier: Apache-2.0
+
+config UART_AESC
+	bool "Aesc Silicon UART driver"
+	default y
+	depends on DT_HAS_AESC_UART_ENABLED
+	select SERIAL_HAS_DRIVER
+	help
+	  Enable the Aesc Silicon UART driver.

drivers/serial/uart_aesc.c

@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2025 Aesc Silicon
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT aesc_uart
+
+#include <errno.h>
+#include <ip_identification.h>
+#include <soc.h>
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/uart.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(aesc_uart, CONFIG_UART_LOG_LEVEL);
+
+struct uart_aesc_data {
+	DEVICE_MMIO_NAMED_RAM(regs);
+};
+
+struct uart_aesc_config {
+	DEVICE_MMIO_NAMED_ROM(regs);
+	uint64_t sys_clk_freq;
+	uint32_t current_speed;
+};
+
+struct uart_aesc_regs {
+	uint32_t data_width;
+	uint32_t sampling_sizes;
+	uint32_t fifo_depths;
+	uint32_t permissions;
+	uint32_t read_write;
+	uint32_t fifo_status;
+	uint32_t clock_div;
+	uint32_t frame_cfg;
+	uint32_t ip;
+	uint32_t ie;
+};
+
+#define DEV_CFG(dev) ((struct uart_aesc_config *)(dev)->config)
+#define DEV_DATA(dev) ((struct uart_aesc_data *)(dev)->data)
+#define DEV_UART(dev)							     \
+	((struct uart_aesc_regs *)DEVICE_MMIO_NAMED_GET(dev, regs))
+
+#define AESC_UART_IRQ_TX_EN			BIT(0)
+#define AESC_UART_IRQ_RX_EN			BIT(1)
+#define AESC_UART_FIFO_TX_COUNT_MASK		GENMASK(23, 16)
+#define AESC_UART_READ_FIFO_VALID_BIT		BIT(16)
+
+static void uart_aesc_poll_out(const struct device *dev, unsigned char c)
+{
+	struct uart_aesc_regs *uart = DEV_UART(dev);
+
+	while ((uart->fifo_status & AESC_UART_FIFO_TX_COUNT_MASK) == 0) {
+		/* Wait until transmit fifo is empty */
+	}
+	uart->read_write = c;
+}
+
+static int uart_aesc_poll_in(const struct device *dev, unsigned char *c)
+{
+	const struct uart_aesc_regs *uart = DEV_UART(dev);
+	int val;
+
+	val = uart->read_write;
+	if (val & AESC_UART_READ_FIFO_VALID_BIT) {
+		*c = val & 0xFF;
+		return 0;
+	}
+
+	return -1;
+}
+
+static int uart_aesc_init(const struct device *dev)
+{
+	const struct uart_aesc_config *cfg = DEV_CFG(dev);
+	volatile uintptr_t *base_addr = (volatile uintptr_t *)DEV_UART(dev);
+	volatile struct uart_aesc_regs *uart;
+
+	DEVICE_MMIO_NAMED_MAP(dev, regs, K_MEM_CACHE_NONE);
+	LOG_DBG("IP core version: %i.%i.%i.",
+		ip_id_get_major_version(base_addr),
+		ip_id_get_minor_version(base_addr),
+		ip_id_get_patchlevel(base_addr)
+	);
+	DEVICE_MMIO_NAMED_GET(dev, regs) = ip_id_relocate_driver(base_addr);
+	LOG_DBG("Relocate driver to address 0x%lx.", DEVICE_MMIO_NAMED_GET(dev, regs));
+	uart = DEV_UART(dev);
+
+	uart->clock_div = cfg->sys_clk_freq / cfg->current_speed / 8;
+	uart->frame_cfg = 7;
+
+	return 0;
+}
+
+static const struct uart_driver_api uart_aesc_driver_api = {
+	.poll_in          = uart_aesc_poll_in,
+	.poll_out         = uart_aesc_poll_out,
+	.err_check        = NULL,
+};
+
+#define AESC_UART_INIT(no)						     \
+	static struct uart_aesc_data uart_aesc_dev_data_##no;		     \
+	static struct uart_aesc_config uart_aesc_dev_cfg_##no = {	     \
+		DEVICE_MMIO_NAMED_ROM_INIT(regs,			     \
+					   DT_INST(no, aesc_uart)),	     \
+		.sys_clk_freq =						     \
+			DT_PROP(DT_INST(no, aesc_uart), clock_frequency),    \
+		.current_speed =					     \
+			DT_PROP(DT_INST(no, aesc_uart), current_speed),	     \
+	};								     \
+	DEVICE_DT_INST_DEFINE(no,					     \
+			      uart_aesc_init,				     \
+			      NULL,					     \
+			      &uart_aesc_dev_data_##no,			     \
+			      &uart_aesc_dev_cfg_##no,			     \
+			      PRE_KERNEL_1,				     \
+			      CONFIG_KERNEL_INIT_PRIORITY_DEVICE,	     \
+			      (void *)&uart_aesc_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(AESC_UART_INIT)

dts/bindings/serial/aesc,uart.yaml

@@ -0,0 +1,21 @@
+#
+# Copyright (c) 2025 Aesc Silicon
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+title: Aesc Silicon UART (Universal Synchronous/Asynchronous Receiver/Transmitter)
+
+description: |
+  The UART (Universal Asynchronous Receiver-Transmitter) IP Core is a configurable serial
+  communication interface designed to handle data transmission and reception. The core includes
+  an internal clock divider and supports flexible frame configurations, allowing for variable data
+  length, parity, and stop bit settings.
+
+compatible: "aesc,uart"
+
+include: uart-controller.yaml
+
+properties:
+  reg:
+    required: true

dts/bindings/vendor-prefixes.txt

@@ -33,6 +33,7 @@ adh	AD Holdings Plc.
 adi	Analog Devices, Inc.
 advantech	Advantech Corporation
 aeroflexgaisler	Aeroflex Gaisler AB
+aesc	Aesc Silicon
 aesop	AESOP Embedded Forum
 al	Annapurna Labs
 alcatel	Alcatel