soc: st: add stm32u535 support #89696
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Hello @harristomy, and thank you very much for your first pull request to the Zephyr project! |
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Sorry, not sure why the line endings for that one file was changed to CRLF, force pushed again just now, hopefully this should be the last push 😓 @erwango |
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dts/arm/st/u5/stm32u535.dtsi
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| / { | ||
| soc { | ||
| /* USB-C PD is not available on this part. */ | ||
| /delete-node/ ucpd@4000dc00; |
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Could you fix the indentation?
dts/arm/st/u5/stm32u535.dtsi
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| num-bidir-endpoints = <8>; | ||
| ram-size = <2048>; | ||
| maximum-speed = "full-speed"; | ||
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x01000000>, |
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prefer STM32_CLOCK(APB2, 24)
dts/arm/st/u5/stm32u535Xi.dtsi
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| / { | ||
| sram0: memory@20000000 { | ||
| /* SRAM1 + SRAM2 */ | ||
| reg = <0x20000000 DT_SIZE_K(256)>; |
dts/arm/st/u5/stm32u535.dtsi
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| / { | ||
| soc { | ||
| /* USB-C PD is not available on this part. */ | ||
| /delete-node/ ucpd@4000dc00; |
dts/arm/st/u5/stm32u535.dtsi
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| num-bidir-endpoints = <8>; | ||
| ram-size = <2048>; | ||
| maximum-speed = "full-speed"; | ||
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x01000000>, |
dts/arm/st/u5/stm32u535Xi.dtsi
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| / { | ||
| sram0: memory@20000000 { | ||
| /* SRAM1 + SRAM2 */ | ||
| reg = <0x20000000 DT_SIZE_K(256)>; |
dts/arm/st/u5/stm32u535.dtsi
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| num-bidir-endpoints = <8>; | ||
| ram-size = <2048>; | ||
| maximum-speed = "full-speed"; | ||
| clocks = <&rcc STM32_CLOCK(APB2, 24) 0x01000000>, |
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remove the 3rd value: macro already STM32_CLOCK() expands to 2 values: bus ID + clock enable bit mask.
dts/arm/st/u5/stm32u535.dtsi
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| ram-size = <2048>; | ||
| maximum-speed = "full-speed"; | ||
| clocks = <&rcc STM32_CLOCK(APB2, 24) 0x01000000>, | ||
| <&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>; |
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Could you indent this line by 1 extra tab?
Adds the u535 soc, similar to the u545 except without the AES HW accelerator signed-off-by: Harris Tomy <harristomy@gmail.com>
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We are using a custom board that uses the STM32U535 SoC, similar to #78910.
This PR adds the necessary modifications to the soc files and addition of the dts files required.
The only difference between this SoC and the 545 is the lack of the HW Encryption module, hence the deletion of the peripheral in the devicetree file.