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@WangHanChi
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Add device tree nodes for the Cadence I2C controllers present in Zynq-7000 SoCs. These I2C controllers are implemented as hard IP blocks in the Processing System (PS) portion of the chip. They are located at 0xe0004000 (i2c0) and 0xe0005000 (i2c1), respectively.

Each node includes standard properties such as compatible strings, memory-mapped address ranges, interrupt configuration, and FIFO depth. Both nodes are marked as "disabled" by default and can be enabled in board-specific overlays depending on application needs.

Reference: UG585 Zynq-7000 SoC TRM
Link: https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM

Add device tree nodes for the Cadence I2C controllers present in
Zynq-7000 SoCs. These I2C controllers are implemented as hard IP
blocks in the Processing System (PS) portion of the chip. They are
located at 0xe0004000 (i2c0) and 0xe0005000 (i2c1), respectively.

Each node includes standard properties such as compatible strings,
memory-mapped address ranges, interrupt configuration, and FIFO
depth. Both nodes are marked as "disabled" by default and can be
enabled in board-specific overlays depending on application needs.

Reference: UG585 Zynq-7000 SoC TRM
Link: https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM

Signed-off-by: Hank Wang <wanghanchi2000@gmail.com>
@sonarqubecloud
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@ibirnbaum
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From my point of view, two preconditions are not fulfilled here:

  1. according to Michal, the driver code needs a fix in order to be compatible with the older version of the I2C IP found in the Zynq-7000 (comp. Add Support for Cadence I2C Driver on kv260_r5 #86400 (comment))
  2. the driver isn't yet compatible with MMU-based systems as the Zynq-7000 is (integration of the DEVICE_MMIO facilities is required first)

@neeliajay
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Hi @WangHanChi,

The driver for Zynq needs to be updated to accommodate the HOLD Bit quirk (you can refer to the Linux implementation for guidance). Additionally, I noticed you're using the compatible string "cdns,i2c-r1p10," but it appears that the driver does not currently utilize this string.

It might be best to first update the driver and then proceed with adding the DTS nodes for Zynq.

@WangHanChi
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@ibirnbaum @neeliajay
Hello, thank you for the suggestions. I will temporarily close this pull request until the driver is ready.

In addition, I will look into the differences between the PS I2C of Zynq and ZynqMP, as I’ve noticed that the examples in Xilinx’s embeddedsw don’t seem to make a clear distinction between the two. Currently, I’m using the PS I2C on a Zynq-7007S to perform some simple read and write operations, and everything is working fine so far.

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4 participants