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  1. add soc mcxa577
  2. add board frdm_mcxa577

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github-actions bot commented Nov 24, 2025

The following west manifest projects have changed revision in this Pull Request:

Name Old Revision New Revision Diff

All manifest checks OK

Note: This message is automatically posted and updated by the Manifest GitHub Action.

@peterwangsz peterwangsz force-pushed the add_frdm_mcxa577_board branch 5 times, most recently from 368e665 to a240666 Compare November 25, 2025 02:18
@peterwangsz peterwangsz force-pushed the add_frdm_mcxa577_board branch 2 times, most recently from 26de469 to 05413c7 Compare December 3, 2025 03:00
@github-actions github-actions bot removed the DNM (manifest) This PR should not be merged (controlled by action-manifest) label Dec 3, 2025
@hakehuang
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the Ci failure is due to #100426

};

&cpu0 {
clock-frequency = <20000000>;
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CLOCK_INIT_CORE_CLOCK is defined as 12MHz, which one is right?

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it should be 12000000, will correct in new commit, thanks.

@@ -0,0 +1,26 @@
/*
* Copyright 2024 NXP
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make sure using right year.

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Several files need be updated.

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will fix in new commit, thanks

interrupts = <31 0>;
clocks = <&syscon MCUX_LPUART0_CLK>;
/* DMA channels 4 and 5, muxed to LPUART RX and TX */
dmas = <&edma0 4 21>, <&edma0 5 22>;
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just confirm the reason behind, why all the lpuart instances share the same dma channel 4 and 5?

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fixed in new commit, thanks for the founding, it was caused by incorrect copy-paste :)


flash: flash@0 {
compatible = "soc-nv-flash";
reg = <0 DT_SIZE_M(2)>;
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In frdm_mcxa577.yaml the flash is 640, here is 2M, is that a mismatch?

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2M is correct, will update frdm_mcxa577.yaml in new commit, thanks.

.. include:: ../../common/board-footer.rst.inc

.. _MCX-A577 SoC Website:
https://www.nxp.com/products/MCX-A34X
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Wrong link.

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will fix in new commit, thanks.

@dleach02 dleach02 removed their assignment Dec 3, 2025
1. add mcxa577 support into hwinfo_mcux_mcx_cmc

Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
#include <soc.h>

/* Core clock frequency: 12MHz in FPGA */
#define CLOCK_INIT_CORE_CLOCK 12000000U
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In index.rst 49, it says "The MCX-A577 SoC is configured to use FRO running at 180MHz as a source for the system clock.", here is 12000000, is that a mismatch?

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it is a problem, will update to 12000000. the 12000000 is for FPGA, need further update after testing with silicon.

===========

The FRDM-MCXA577 SoC has 4 LPUART interfaces for serial communication.
LPUART 2 is configured as UART for the console.
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lpuart0?

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should be LPUART0, will update in new commit

Hardware
********

- MCX-A577 Arm Cortex-M33 microcontroller running at 180 MHz
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clock frequency not matched.

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will updated in new commit to align with clock configure in source code.


reset: reset {
compatible = "nxp,lpc-syscon-reset";
#reset-cells = <1>;
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just confirm, does any driver support resets? if yes, please add the reset line in the node.

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Did not find driver support the reset, so not add the reset line in current commit.

1. add soc mcxa577
2. add board frdm_mcxa577

Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
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sonarqubecloud bot commented Dec 4, 2025

@decsny decsny removed their request for review December 4, 2025 19:00
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8 participants