x86_64: Implement integer saturating left shifting codegen

[xtexx]

Simliarly to shl_with_overflow, we first SHL/SAL the integer, then SHR/SAR it back to compare if overflow happens.
If overflow happened, set result to the upper limit to make it saturating.

Theoretically, if the left shifting instruction is lowered as a single SHL/SAL opcode, and the left operand fits into a register (so no truncation is needed), the CF flag can be used to check for overflow. However the optimization is not implemented right now (for my laziness).

Bug: #17645

[xtexx]

What's the CI error. It seems that I didn't touch that region of code.

[mlugg]

Don't mind that failure -- it's an inconsistent issue which is being debugged as I type this. Once it's fixed, a rebase should solve that error.

[jacobly0]

I don't like that this introduces a miscomp, I would rather the backend error on unsupported types rather than silently produce incorrect code.

[xtexx]

@jacobly0 which unsupported types? there is already a compiler error when unsupported type is hit.

https://github.com/ziglang/zig/blob/ec2df79cbf25e53c79d53dd6d461bd9d7457bd85/src/arch/x86_64/CodeGen.zig#L12944-L12946

[jacobly0]

$ cat check.zig
const std = @import("std");

fn shlSat(x: anytype, y: std.math.Log2Int(@TypeOf(x))) @TypeOf(x) {
    return x <<| y;
}

fn testType(comptime T: type) bool {
    var ok = true;
    comptime var rhs: std.math.Log2Int(T) = 0;
    inline while (true) : (rhs += 1) {
        comptime var lhs: T = std.math.minInt(T);
        inline while (true) : (lhs += 1) {
            ok = shlSat(lhs, rhs) == lhs <<| rhs and ok;
            if (lhs == std.math.maxInt(T)) break;
        }
        if (rhs == @bitSizeOf(T) - 1) break;
    }
    return ok;
}

pub fn main() void {
    var ok = true;
    ok = testType(i2) and ok;
    ok = testType(u2) and ok;
    ok = testType(i3) and ok;
    ok = testType(u3) and ok;
    ok = testType(i4) and ok;
    ok = testType(u4) and ok;
    std.debug.print("{s}\n", .{if (ok) "ok" else "bad"});
}
$ zig run -fllvm check.zig
ok
$ zig run -fno-llvm check.zig
bad

[xtexx]

@jacobly0 ahh! Sorry for my mistake and thanks for your careful review!

I forgot that negative values need the minimum value to saturate and it seems that the saturating_arithmetic.zig behavior test is not strong enough. The force-push above should solve the error and the check you have given is passing successfully.

However, x86 does not have a saturating shifting instruction so we have to emit up to two shifting and two conditional branches, totally ~10 MIR instructions, I doubt if the shl_sat grammar and IR is useful, as it seems to be a pretty rare case.

[jacobly0]

Looks good enough to get in the next release, if I don't manage to finish the rewrite before then.

[jacobly0]

While rewriting comparisons, I have added Temp.cmpInts in #22637. If you want, you can see other uses in the file for how to integrate it with other legacy code. It handles turning any passed in condition into a functional result flag.

[jacobly0]

A missing instruction is causing a miscomp of:

const std = @import("std");
var lhs: i256 = -0x53d4148cee74ea43477a65b3daa7b8fdadcbf4508e793f4af113b8d8da5a7eb6;
var rhs: u8 = 0x91;
pub fn main() void {
    std.debug.print("{} <<| {} == {}\n", .{ lhs, rhs, lhs <<| rhs });
}

$ zig run -fllvm repro.zig
-37916679844576018420322620862767642147218730393747648456860519430618437287606 <<| 145 == -57896044618658097711785492504343953926634992332820282019728792003956564819968
$ zig run -fno-llvm repro.zig
-37916679844576018420322620862767642147218730393747648456860519430618437287606 <<| 145 == 57896044618658097711785492504343953926634992332820282019728792003956564819967

Fixed by:

@@ -88544,7 +88548,7 @@ fn genShiftBinOpMir(
 ) !void {
     const pt = self.pt;
     const zcu = pt.zcu;
-    const abi_size: u32 = @intCast(lhs_ty.abiSize(zcu));
+    const abi_size: u31 = @intCast(lhs_ty.abiSize(zcu));
     const shift_abi_size: u32 = @intCast(rhs_ty.abiSize(zcu));
     try self.spillEflagsIfOccupied();
 
@@ -88728,7 +88732,17 @@ fn genShiftBinOpMir(
                 .immediate => {},
                 else => self.performReloc(skip),
             }
-        }
+        } else try self.asmRegisterMemory(.{ ._, .mov }, temp_regs[2].to64(), .{
+            .base = .{ .frame = lhs_mcv.load_frame.index },
+            .mod = .{ .rm = .{
+                .size = .qword,
+                .disp = switch (tag[0]) {
+                    ._l => lhs_mcv.load_frame.off,
+                    ._r => lhs_mcv.load_frame.off + abi_size - 8,
+                    else => unreachable,
+                },
+            } },
+        });
         switch (rhs_mcv) {
             .immediate => |shift_imm| try self.asmRegisterImmediate(
                 tag,

---

Also, there is no handling for shift amounts larger than the bit width:

const std = @import("std");
var lhs: u8 = 0xab;
var rhs: u8 = 32;
pub fn main() void {
    std.debug.print("{} <<| {} == {}\n", .{ lhs, rhs, lhs <<| rhs });
}

$ zig run -fllvm repro.zig
171 <<| 32 == 255
$ zig run -fno-llvm repro.zig
171 <<| 32 == 171

Normally I would suggest looking at the llvm backend lowering, but even that miscomps. As usual, adding a check for this case to emit an error instead of a miscomp would make this PR mergeable.

[xtexx]

Applied you fix for the missing instruction. Thank you!
While RHS may not be an immediate/literal constant, how can the miscomp case be checked at compile-time?

[jacobly0]

Based on x86_64 semantics, you have only implemented the following cases:

• lhs_bits <= 32 and rhs_bits <= 5
• lhs_bits > 32 and lhs_bits <= 64 and rhs_bits <= 6
• rhs_bits <= log2(lhs_bits)

[xtexx]

The genShiftBinOpMir diff mentioned above sometimes fails to encode:

error(x86_64_encoder): no encoding found for: none mov m128 imm8s none none

[jacobly0]

That's unrelated to my diff, the instruction I added is neither .size = .xword nor contains an immediate.

[xtexx]

oops, sorry. It is my mistake.

[jacobly0]

Just a heads up, given all of the miscomps I have already found, this is going to need more behavior test coverage than just enabling an already existing test. At least regression tests covering the examples that have been mentioned should be added near the enabled behavior test.

[xtexx]

Just out of curiosity, how do you find some many cases (which looked like random to me) for testing?

[jacobly0]

The bits are just copied from other random values, not very relevant to the miscomps. I just tried various combinations of type widths, signedness, and shift amounts that either overflow or not.

[jacobly0]

Otherwise looks good, I know some people have been waiting for this operation for a while.