Skip to content
View zr93837746's full-sized avatar

Block or report zr93837746

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. -DFT-STM32-IEEE-1149.1-BSDL -DFT-STM32-IEEE-1149.1-BSDL Public

    **低成本替代方案:** 针对产线测试成本高的问题,设计了一款基于 **STM32** 的 JTAG 控制方案,旨在替代昂贵的商业 ATE 设备 (如 **GOEPEL**) 进行 PCB 互连测试。**协议底层实现:** 摒弃标准库,直接操作 GPIO 模拟 JTAG 时序 (TCK, TMS, TDI, TDO),实现了一个标准的 **16 状态 TAP 控制器**,深入理解了 DFT…

    Shell

  2. Implementing-Boundary-Scan-for-STM32-and-D60E-Using-OpenOCD-and-OpenJTAG Implementing-Boundary-Scan-for-STM32-and-D60E-Using-OpenOCD-and-OpenJTAG Public

  3. - - Public

  4. edge-ai-riscv-fpga edge-ai-riscv-fpga Public

    A lightweight RISC-V SoC deployed on FPGA, featuring a custom 2x2 systolic array AI accelerator with wavefront scheduling and bare-metal C drivers built using LiteX.

    C