v0.3.1+amd.1

v0.3.1+amd.1

Updated Upstream

• Updated to upstream v0.3.1 tag of FlashInfer (#156) @diptorupd

Added

• Add AITER backend support for FlashInfer SinglePrefill (#167) @rtmadduri
• Add AITER backend support for FlashInfer BatchPrefill (#161) @rtmadduri
• Port sampling module (OnlineSoftmax / SamplingFromLogits) to HIP (#102, #163) @demandal25, @diptorupd
• Port quantization module to ROCm/HIP (#145) @diptorupd
• Enable activation kernels on v0.3.1 API (#165) @diptorupd
• Add ROCm-specific logits_processor test case (#166) @diptorupd
• Add cuda graph support for paged batch prefill (#135, #138) @demandal25
• Add device_utils for HIP/CUDA device identification (#149) @diptorupd
• Initial infrastructure for AMD-specific code coverage automation (#128) @diptorupd

Changed

• Port over upstream's latest AOT infrastructure to amd-flashinfer (#123) @diptorupd
• Isolate HIP kernels in dedicated csrc_rocm directory (#144) @diptorupd
• Remove CUDA sections from pytorch_hip (#143) @diptorupd
• Refactor sampling.cuh to unified CUDA/HIP header (#147) @diptorupd
• Refactor pytorch.py to increase coverage (#132) @demandal25
• Port HIP unit tests to v0.3.1 API @diptorupd
• Updates coverage script to identify unmodified but tested modules (#157) @diptorupd
• Update README with published docker images (#137) @demandal25

Removed

• Remove cascade attention support (not supported on ROCm) (#129, #130) @demandal25

Fixed

• Fix device contextmanager to use per-call context instead of setting default globally (#146) @diptorupd
• Fix minor issues in pytorch_hip.py @diptorupd

Maintenance

• Tech debt reduction: remove superficial diffs and unused code (#152, #153) @diptorupd
• Update pre-commit hooks with AMD-specific configuration @diptorupd

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Contributors: @diptorupd, @demandal25, @rtmadduri

Summary: This release updates amd-flashinfer to use the upstream v0.3.1 tag and adds significant new functionality. Key additions include AITER backend support for both single and batch prefill, full sampling and quantization module ports to ROCm/HIP, and CUDA graph support for paged batch prefill. Infrastructure improvements include isolation of HIP kernels into a dedicated csrc_rocm directory, updated AOT build infrastructure, and initial AMD-specific code coverage tooling.