rv/sg204x: update patchset #13

RevySR · 2025-10-10T00:59:29Z

No description provided.

…_[startup|shutdown]_parent()" This reverts commit 07b64e9.

This reverts commit 14b3fb2.

This reverts commit 761e9c6.

…s for SG2044" This reverts commit 7fd8539.

This reverts commit 1361f63.

This reverts commit 666e16e.

This reverts commit e35a219.

…g affinity" This reverts commit f8237b9.

This reverts commit 855ac46.

…s_mmap" This reverts commit f2f09f1.

This reverts commit ba538ba.

This reverts commit d0253a4.

This reverts commit 6060c57.

This reverts commit cc98996.

The variable type of offset should be consistent with the relevant interfaces of mmap which described in commit 295f100 ("syscalls: mmap(): use unsigned offset type consistently"). Otherwise, a user input with the top bit set would result in a negative page offset rather than a large one. Signed-off-by: Jessica Liu <liu.xuemei1@zte.com.cn> Tested-by: Han Gao <rabenda.cn@gmail.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Link: https://lore.kernel.org/r/20250801104948133AaMr5S6E382PbNNhoJgHA@zte.com.cn [pjw@kernel.org: hand-applied mangled patch; fixed checkpatch error] Signed-off-by: Paul Walmsley <pjw@kernel.org> (cherry picked from commit 316b60b) Signed-off-by: Han Gao <rabenda.cn@gmail.com>

Compared with IO attributes, NC attributes can improve performance, specifically in these aspects: Relaxed Order, Gathering, Supports Read Speculation, Supports Unaligned Access. Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com> Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20250722091504.45974-2-cuiyunhui@bytedance.com Signed-off-by: Paul Walmsley <pjw@kernel.org> (cherry picked from commit 3a8ee3a) Signed-off-by: Han Gao <rabenda.cn@gmail.com>

plic_set_affinity() always calls plic_irq_enable(), which clears up the priority setting even the interrupt is only masked. This unmasks the interrupt unexpectly. Replace the plic_irq_enable/disable() with plic_irq_toggle() to avoid changing the priority setting. Suggested-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Nam Cao <namcao@linutronix.de> # VisionFive 2 Tested-by: Chen Wang <unicorn_wang@outlook.com> # Pioneerbox Reviewed-by: Nam Cao <namcao@linutronix.de> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/all/20250811002633.55275-1-inochiama@gmail.com Link: https://lore.kernel.org/lkml/20250722224513.22125-1-inochiama@gmail.com/ (cherry picked from commit adecf78) Signed-off-by: Han Gao <rabenda.cn@gmail.com>

As the MSI controller on SG2044 uses PLIC as the underlying interrupt controller, it needs to call irq_enable() and irq_disable() to startup/shutdown interrupts. Otherwise, the MSI interrupt can not be startup correctly and will not respond any incoming interrupt. Introduce irq_chip_startup_parent() and irq_chip_shutdown_parent() to allow the interrupt controller to call the irq_startup()/irq_shutdown() callbacks of the parent interrupt chip. In case the irq_startup()/irq_shutdown() callbacks are not implemented for the parent interrupt chip, this will fallback to irq_chip_enable_parent() or irq_chip_disable_parent(). Suggested-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Chen Wang <unicorn_wang@outlook.com> # Pioneerbox Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/all/20250813232835.43458-2-inochiama@gmail.com Link: https://lore.kernel.org/lkml/20250722224513.22125-1-inochiama@gmail.com/ (cherry picked from commit 7a721a2) Signed-off-by: Han Gao <rabenda.cn@gmail.com>

As the RISC-V PLIC cannot apply affinity settings without invoking irq_enable(), it will make the interrupt unavailble when used as an underlying interrupt chip for the MSI controller. Implement the irq_startup() and irq_shutdown() callbacks for the PCI MSI and MSI-X templates. For chips that specify MSI_FLAG_PCI_MSI_STARTUP_PARENT, the parent startup and shutdown functions are invoked. That allows the interrupt on the parent chip to be enabled if the interrupt has not been enabled during allocation. This is necessary for MSI controllers which use PLIC as underlying parent interrupt chip. Suggested-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Chen Wang <unicorn_wang@outlook.com> # Pioneerbox Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/all/20250813232835.43458-3-inochiama@gmail.com (cherry picked from commit 54f45a3) Signed-off-by: Han Gao <rabenda.cn@gmail.com>

When using NVME on SG2044, the NVME drvier always complains about "I/O tag XXX (XXX) QID XX timeout, completion polled", which is caused by the broken affinity setting mechanism of the sg2042-msi driver. The PLIC driver can only the set the affinity when enabled, but the sg2042-msi driver invokes the affinity setter in disabled state, which causes the change to be lost. Cure this by implementing the irq_startup()/shutdown() callbacks, which allow to startup (enabled) the underlying PLIC first. Fixes: e96b93a ("irqchip/sg2042-msi: Add the Sophgo SG2044 MSI interrupt controller") Reported-by: Han Gao <rabenda.cn@gmail.com> Suggested-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Chen Wang <unicorn_wang@outlook.com> # Pioneerbox Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/all/20250813232835.43458-4-inochiama@gmail.com (cherry picked from commit 9d8c418) Signed-off-by: Han Gao <rabenda.cn@gmail.com>

…2044 The MSI controller on SG2044 has the ability to allocate multiple PCI MSI interrupts. So the PCIe controller driver can use this feature if the hardware supports multiple PCI MSI interrupts. Add the MSI_FLAG_MULTI_PCI_MSI flag to the supported_flags of SG2044 msi_parent_ops to enable this functionality. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Chen Wang <unicorn_wang@outlook.com> # Pioneerbox Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/all/20250813232835.43458-5-inochiama@gmail.com (cherry picked from commit 7ee4a5a) Signed-off-by: Han Gao <rabenda.cn@gmail.com>

…p|shutdown]_parent() For MSI controllers which only support MSI_FLAG_PCI_MSI_MASK_PARENT, the newly added callback irq_startup() and irq_shutdown() for pci_msi[x]_template will not unmask or mask the interrupt when startup() resp. shutdown() is invoked. This prevents the interrupt from being enabled resp. disabled. Invoke irq_[un]mask_parent() in cond_[startup|shutdown]_parent(), when the interrupt has the MSI_FLAG_PCI_MSI_MASK_PARENT flag set. Fixes: 54f45a3 ("PCI/MSI: Add startup/shutdown for per device domains") Reported-by: Linux Kernel Functional Testing <lkft@linaro.org> Reported-by: Nathan Chancellor <nathan@kernel.org> Reported-by: Wei Fang <wei.fang@nxp.com> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Nathan Chancellor <nathan@kernel.org> Tested-by: Linux Kernel Functional Testing <lkft@linaro.org> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Wei Fang <wei.fang@nxp.com> Tested-by: Chen Wang <unicorn_wang@outlook.com> # Pioneerbox/SG2042 Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/all/20250827230943.17829-1-inochiama@gmail.com Closes: https://lore.kernel.org/regressions/aK4O7Hl8NCVEMznB@monster/ Closes: https://lore.kernel.org/regressions/20250826220959.GA4119563@ax162/ Closes: https://lore.kernel.org/all/20250827093911.1218640-1-wei.fang@nxp.com/ (cherry picked from commit 727e914) Signed-off-by: Han Gao <rabenda.cn@gmail.com>

Move vendor errata definitions into errata_list_vendors.h. Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Tested-by: Han Gao <rabenda.cn@gmail.com> Link: https://lore.kernel.org/r/20250713155321.2064856-2-guoren@kernel.org [pjw@kernel.org: updated to apply and to make the whitespace consistent] Signed-off-by: Paul Walmsley <pjw@kernel.org> (cherry picked from commit 16d18e3) Signed-off-by: Han Gao <rabenda.cn@gmail.com>

According to the description of [1], sg2042 is divided into 4 numa. STREAM test performance will improve. Before: Function Best Rate MB/s Avg time Min time Max time Copy: 10739.7 0.015687 0.014898 0.016385 Scale: 10865.9 0.015628 0.014725 0.016757 Add: 10622.3 0.023276 0.022594 0.023899 Triad: 10583.4 0.023653 0.022677 0.024761 After: Function Best Rate MB/s Avg time Min time Max time Copy: 34254.9 0.005142 0.004671 0.005995 Scale: 37735.5 0.004752 0.004240 0.005407 Add: 44206.8 0.005983 0.005429 0.006461 Triad: 43040.6 0.006320 0.005576 0.006996 [1] https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/pic/mesh.png Signed-off-by: Han Gao <rabenda.cn@gmail.com> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/20250910105531.519897-1-rabenda.cn@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> (cherry picked from commit 4d94abd) Signed-off-by: Han Gao <rabenda.cn@gmail.com>

Add binding for Sophgo SG2042 PCIe host controller. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/2755f145755b6096247c26852b63671a6fea4dbf.1757643388.git.unicorn_wang@outlook.com (cherry picked from commit 4e4a4f5) Signed-off-by: Han Gao <rabenda.cn@gmail.com>

…ore using it cdns_pcie::ops might not be populated by all the Cadence glue drivers. This is going to be true for the upcoming Sophgo platform which doesn't set the ops. Hence, add a check to prevent NULL pointer dereference. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> [mani: reworded subject and description] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/35182ee1d972dfcd093a964e11205efcebbdc044.1757643388.git.unicorn_wang@outlook.com (cherry picked from commit 49a6c16) Signed-off-by: Han Gao <rabenda.cn@gmail.com>

Add support for PCIe controller in Sophgo SG2042 SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence* common driver. The PCIe controller in SG2042 works in host mode only, supporting data rate up to 16 GT/s and lanes up to x16 or x8. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> [mani: reworded description and minor code cleanups] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/01b0a57cd9dba8bed7c1f2d52997046c2c6f042b.1757643388.git.unicorn_wang@outlook.com (cherry picked from commit 1c72774) Signed-off-by: Han Gao <rabenda.cn@gmail.com>

Change the return value of match_noXlvl() to return the SATP mode that will be used, rather than the mode being disabled. This enables unified logic for return value judgement with the function that obtains mmu-type from the fdt, avoiding extra conversion. This only changes the naming, with no functional impact. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Link: https://lore.kernel.org/r/20250722-satp-from-fdt-v1-1-5ba22218fa5f@pigmoral.tech Signed-off-by: Paul Walmsley <pjw@kernel.org> (cherry picked from commit f3243be) Signed-off-by: Han Gao <rabenda.cn@gmail.com>

Some RISC-V implementations may hang when attempting to write an unsupported SATP mode, even though the latest RISC-V specification states such writes should have no effect. To avoid this issue, the logic for selecting SATP mode has been refined: The kernel now determines the SATP mode limit by taking the minimum of the value specified by the kernel command line (noXlvl) and the "mmu-type" property in the device tree (FDT). If only one is specified, use that. - If the resulting limit is sv48 or higher, the kernel will probe SATP modes from this limit downward until a supported mode is found. - If the limit is sv39, the kernel will directly use sv39 without probing. This ensures SATP mode selection is safe and compatible with both hardware and user configuration, minimizing the risk of hangs. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Link: https://lore.kernel.org/r/20250722-satp-from-fdt-v1-2-5ba22218fa5f@pigmoral.tech Signed-off-by: Paul Walmsley <pjw@kernel.org> (cherry picked from commit 17e9521) Signed-off-by: Han Gao <rabenda.cn@gmail.com>

The early version of XuanTie C910 core has a store merge buffer delay problem. The store merge buffer could improve the store queue performance by merging multi-store requests, but when there are not continued store requests, the prior single store request would be waiting in the store queue for a long time. That would cause significant problems for communication between multi-cores. This problem was found on sg2042 & th1520 platforms with the qspinlock lock torture test. So appending a fence w.o could immediately flush the store merge buffer and let other cores see the write result. This will apply the WRITE_ONCE errata to handle the non-standard behavior via appending a fence w.o instruction for WRITE_ONCE(). This problem is only observed on the sg2042 hardware platform by running the lock_torture test program for half an hour. The problem was not found in the user space application, because interrupt can break the livelock. Reviewed-by: Leonardo Bras <leobras@redhat.com> Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org> Link: https://lore.kernel.org/r/20250713155321.2064856-3-guoren@kernel.org Signed-off-by: Han Gao <rabenda.cn@gmail.com>

RISC-V Svpbmt Standard Extension for Page-Based Memory Types defines three modes: Mode | Value | Requested Memory Attributes PMA | 0 | None NC | 1 | Non-cacheable, idempotent, weakly-ordered (RVWMO), | | main memory IO | 2 | Non-cacheable, non-idempotent, strongly-ordered | | (I/O ordering), I/O The pgprot_dmacoherent default uses the IO memory attribute if there is no asm definition, but IO is not for main memory according to Svpbmt rules. This commit corrects pgprot_dmacoherent with the NC memory attribute, which satisfies performance improvement and prevents using the IO attribute to access main memory. Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org> Link: https://lore.kernel.org/r/20251011155746.1558731-1-guoren@kernel.org Signed-off-by: Han Gao <rabenda.cn@gmail.com>

t8103: - WLAN (SMC PMU GPIO #13) Signed-off-by: Hector Martin <marcan@marcan.st>

- WLAN (SMC PMU GPIO #13) - SD (SMC PMU GPIO torvalds#26) Signed-off-by: Hector Martin <marcan@marcan.st>

…resize Resizing BAR to a larger size has to release upstream bridge windows in order make the bridge windows larger as well (and to potential relocate them into a larger free block within iomem space). Some GPUs have an integrated PCI switch that has BAR0. The resource allocation assigns space for that BAR0 as it does for any resource. An extra resource on a bridge will pin its upstream bridge window in place which prevents BAR resize for anything beneath that bridge. Nothing in the pcieport driver provided by PCI core, which typically is the driver bound to these bridges, requires that BAR0. Because of that, releasing the extra BAR does not seem to have notable downsides but comes with a clear upside. Therefore, release BAR0 of such switches using a quirk and clear its flags to prevent any new invocation of the resource assignment algorithm from assigning the resource again. Due to other siblings within the PCI hierarchy of all the devices integrated into the GPU, some other devices may still have to be manually removed before the resize is free of any bridge window pins. Such siblings can be released through sysfs to unpin windows while leaving access to GPU's sysfs entries required for initiating the resize operation, whereas removing the topmost bridge this quirk targets would result in removing the GPU device as well so no manual workaround for this problem exists. Reported-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/linux-pci/fl6tx5ztvttg7txmz2ps7oyd745wg3lwcp3h7esmvnyg26n44y@owo2ojiu2mov/ Link: https://lore.kernel.org/intel-xe/20250721173057.867829-1-uwu@icenowy.me/ Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Cc: stable@vger.kernel.org # v6.12+ Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/intel-xe/fafda2a3-fc63-ce97-d22b-803f771a4d19@linux.intel.com Link: https://lore.kernel.org/r/20250918-xe-pci-rebar-2-v1-1-6c094702a074@intel.com Signed-off-by: Han Gao <rabenda.cn@gmail.com>

Read the device tree configuration and use it to set the interrupt type. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Inochi Amaoto <inochiama@gmail.com> # Sophgo SRD3-10 Link: https://lore.kernel.org/all/b22d2b0a00a96161253435d17b3c66538f3ba1c2.1756953919.git.unicorn_wang@outlook.com (cherry picked from commit c2616c5) Signed-off-by: Han Gao <rabenda.cn@gmail.com>

…_EDGE_RISING Fix msi irq type to be the correct type, although this field is not used yet. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/831c1b650c575380d56ef3e2faed9bee278c9006.1756953919.git.unicorn_wang@outlook.com (cherry picked from commit a4bd4c3) Signed-off-by: Han Gao <rabenda.cn@gmail.com>

…_EDGE_RISING Fix msi irq type to be the correct type, although this field is not used yet. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Inochi Amaoto <inochiama@gmail.com> # Sophgo SRD3-10 Link: https://lore.kernel.org/all/c38b9b1682af978473705b7e70b6faaa36fe5024.1756953919.git.unicorn_wang@outlook.com (cherry picked from commit 8aefd27) Signed-off-by: Han Gao <rabenda.cn@gmail.com>

T-HEAD C920 has a V2 iteration, which supports Sscompmf. The V2 iteration supports the same perf events as V1. Reuse T-HEAD c900-legacy JSON file for T-HEAD C920V2. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/r/20251014014830.613399-1-inochiama@gmail.com Signed-off-by: Han Gao <rabenda.cn@gmail.com>

MingcongBai · 2025-10-14T08:55:19Z

Now part of aosc/v6.17.3-rc1. Thanks!

- Refresh Loongson UART patchset to v6. - Refresh Surface patchset to 6.17. - Refresh SG2042/2044 patchset.[^1] - Backport a fix for unusable Intel VMD with v6.18-rc1.[^2] - Backport Loongson AVEC and AVEC redirect controller. - (all) Refresh configs. - (all) Bump rustc version to 109000 (1.90.0). - Track patches at AOSC-Tracking/linux @ aosc/v6.18-rc1 (HEAD: 6e56b1c4a595e038fd2dce985898798712ff6982). [^1]: AOSC-Tracking/linux#13 [^2]: https://lore.kernel.org/all/20251014014607.612586-1-inochiama@gmail.com/

- Refresh Loongson UART patchset to v6. - Refresh Surface patchset to 6.17. - Refresh SG2042/2044 patchset.[^1] - Backport a fix for unusable Intel VMD with v6.18-rc1.[^2] - Backport a fix for build failure on LoongArch.[^3] - Backport a fix for Haptic Touchpad symbol export issue.[^4] - Backport support for Loongson AVEC (KVM) and AVEC redirect controller. - (all) Refresh configs. - (all) Bump rustc version to 109000 (1.90.0). - Track patches at AOSC-Tracking/linux @ aosc/v6.18-rc1 (HEAD: 852f44caf0d77e689bc4502128d787f0aa7628cc). [^1]: AOSC-Tracking/linux#13 [^2]: https://lore.kernel.org/all/20251014014607.612586-1-inochiama@gmail.com/ [^3]: https://lore.kernel.org/loongarch/20251015022037.14535-2-xry111@xry111.site/ [^4]: https://lore.kernel.org/all/20251013-hid-haptic-kconfig-fix-v1-1-b1ad90732625@google.com/

- Refresh Loongson UART patchset to v6. - Refresh Surface patchset to 6.17. - Refresh SG2042/2044 patchset.[^1] - Backport a fix for unusable Intel VMD with v6.18-rc1.[^2] - Backport a fix for build failure on LoongArch.[^3] - Backport a fix for Haptic Touchpad symbol export issue.[^4] - Backport support for Loongson AVEC (KVM) and AVEC redirect controller. - (all) Refresh configs. - (all) Bump rustc version to 109000 (1.90.0). - Track patches at AOSC-Tracking/linux @ aosc/v6.18-rc1 (HEAD: 213107bbe1895b133f4cc3751d357279223071e7). [^1]: AOSC-Tracking/linux#13 [^2]: https://lore.kernel.org/all/20251014014607.612586-1-inochiama@gmail.com/ [^3]: https://lore.kernel.org/loongarch/20251015022037.14535-2-xry111@xry111.site/ [^4]: https://lore.kernel.org/all/20251013-hid-haptic-kconfig-fix-v1-1-b1ad90732625@google.com/

[ Upstream commit 48918ca ] The test starts a workload and then opens events. If the events fail to open, for example because of perf_event_paranoid, the gopipe of the workload is leaked and the file descriptor leak check fails when the test exits. To avoid this cancel the workload when opening the events fails. Before: ``` $ perf test -vv 7 7: PERF_RECORD_* events & perf_sample fields: --- start --- test child forked, pid 1189568 Using CPUID GenuineIntel-6-B7-1 ------------------------------------------------------------ perf_event_attr: type 0 (PERF_TYPE_HARDWARE) config 0xa00000000 (cpu_atom/PERF_COUNT_HW_CPU_CYCLES/) disabled 1 ------------------------------------------------------------ sys_perf_event_open: pid 0 cpu -1 group_fd -1 flags 0x8 sys_perf_event_open failed, error -13 ------------------------------------------------------------ perf_event_attr: type 0 (PERF_TYPE_HARDWARE) config 0xa00000000 (cpu_atom/PERF_COUNT_HW_CPU_CYCLES/) disabled 1 exclude_kernel 1 ------------------------------------------------------------ sys_perf_event_open: pid 0 cpu -1 group_fd -1 flags 0x8 = 3 ------------------------------------------------------------ perf_event_attr: type 0 (PERF_TYPE_HARDWARE) config 0x400000000 (cpu_core/PERF_COUNT_HW_CPU_CYCLES/) disabled 1 ------------------------------------------------------------ sys_perf_event_open: pid 0 cpu -1 group_fd -1 flags 0x8 sys_perf_event_open failed, error -13 ------------------------------------------------------------ perf_event_attr: type 0 (PERF_TYPE_HARDWARE) config 0x400000000 (cpu_core/PERF_COUNT_HW_CPU_CYCLES/) disabled 1 exclude_kernel 1 ------------------------------------------------------------ sys_perf_event_open: pid 0 cpu -1 group_fd -1 flags 0x8 = 3 Attempt to add: software/cpu-clock/ ..after resolving event: software/config=0/ cpu-clock -> software/cpu-clock/ ------------------------------------------------------------ perf_event_attr: type 1 (PERF_TYPE_SOFTWARE) size 136 config 0x9 (PERF_COUNT_SW_DUMMY) sample_type IP|TID|TIME|CPU read_format ID|LOST disabled 1 inherit 1 mmap 1 comm 1 enable_on_exec 1 task 1 sample_id_all 1 mmap2 1 comm_exec 1 ksymbol 1 bpf_event 1 { wakeup_events, wakeup_watermark } 1 ------------------------------------------------------------ sys_perf_event_open: pid 1189569 cpu 0 group_fd -1 flags 0x8 sys_perf_event_open failed, error -13 perf_evlist__open: Permission denied ---- end(-2) ---- Leak of file descriptor 6 that opened: 'pipe:[14200347]' ---- unexpected signal (6) ---- iFailed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon Failed to read build ID for //anon #0 0x565358f6666e in child_test_sig_handler builtin-test.c:311 #1 0x7f29ce849df0 in __restore_rt libc_sigaction.c:0 #2 0x7f29ce89e95c in __pthread_kill_implementation pthread_kill.c:44 #3 0x7f29ce849cc2 in raise raise.c:27 #4 0x7f29ce8324ac in abort abort.c:81 #5 0x565358f662d4 in check_leaks builtin-test.c:226 #6 0x565358f6682e in run_test_child builtin-test.c:344 #7 0x565358ef7121 in start_command run-command.c:128 #8 0x565358f67273 in start_test builtin-test.c:545 #9 0x565358f6771d in __cmd_test builtin-test.c:647 #10 0x565358f682bd in cmd_test builtin-test.c:849 #11 0x565358ee5ded in run_builtin perf.c:349 #12 0x565358ee6085 in handle_internal_command perf.c:401 #13 0x565358ee61de in run_argv perf.c:448 #14 0x565358ee6527 in main perf.c:555 torvalds#15 0x7f29ce833ca8 in __libc_start_call_main libc_start_call_main.h:74 torvalds#16 0x7f29ce833d65 in __libc_start_main@@GLIBC_2.34 libc-start.c:128 torvalds#17 0x565358e391c1 in _start perf[851c1] 7: PERF_RECORD_* events & perf_sample fields : FAILED! ``` After: ``` $ perf test 7 7: PERF_RECORD_* events & perf_sample fields : Skip (permissions) ``` Fixes: 16d00fe ("perf tests: Move test__PERF_RECORD into separate object") Signed-off-by: Ian Rogers <irogers@google.com> Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Athira Rajeev <atrajeev@linux.ibm.com> Cc: Chun-Tse Shao <ctshao@google.com> Cc: Howard Chu <howardchu95@gmail.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@linaro.org> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> Signed-off-by: Sasha Levin <sashal@kernel.org>

- Refresh Loongson UART patchset to v6. - Refresh Surface patchset to 6.17. - Refresh SG2042/2044 patchset.[^1] - Backport an upstream fix for ACPI access error on RISC-V ACPI+DT platforms.[^2] - Refresh kernel configurations. - Revert to using deepin-origin KVM fixes for 3B6000 and 3C6000 families. - Track patches at AOSC-Tracking/linux @ aosc/v6.17.5-rc2 (HEAD: fbe142c47f94449ccc552bdee576361edc57cf81). [^1]: AOSC-Tracking/linux#13 [^2]: AOSC-Tracking/linux#14

- Refresh Loongson UART patchset to v6. - Refresh Surface patchset to 6.17. - Refresh SG2042/2044 patchset.[^1] - Backport an upstream fix for ACPI access error on RISC-V ACPI+DT platforms.[^2] - Refresh kernel configurations. - Revert to using deepin-origin KVM fixes for 3B6000 and 3C6000 families. - (loongarch64) Backport a fix for rust-bindgen failure. - Track patches at AOSC-Tracking/linux @ aosc/v6.17.5- (HEAD: 84c080e43bd2970b617f9c5a7e44224791c9be21). [^1]: AOSC-Tracking/linux#13 [^2]: AOSC-Tracking/linux#14

RevySR and others added 30 commits October 10, 2025 08:50

Revert "FROMLIST: PCI/MSI: Check MSI_FLAG_PCI_MSI_MASK_PARENT in cond…

146ed89

…_[startup|shutdown]_parent()" This reverts commit 07b64e9.

Revert "FROMLIST: riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup"

a6c3687

This reverts commit 14b3fb2.

Revert "FROMLIST: riscv: Move vendor errata definitions to new header"

aa3cc33

This reverts commit 761e9c6.

Revert "FROMLIST: irqchip/sg2042-msi: Set MSI_FLAG_MULTI_PCI_MSI flag…

315b016

…s for SG2044" This reverts commit 7fd8539.

Revert "FROMLIST: irqchip/sg2042-msi: Fix broken affinity setting"

0e936ba

This reverts commit 1361f63.

Revert "FROMLIST: PCI/MSI: Add startup/shutdown for per device domains"

6f10a57

This reverts commit 666e16e.

Revert "FROMLIST: genirq: Add irq_chip_(startup/shutdown)_parent()"

b66db21

This reverts commit e35a219.

Revert "FROMLIST: irqchip/sifive-plic: Respect mask state when settin…

839c3d8

…g affinity" This reverts commit f8237b9.

Revert "FROMLIST: riscv: introduce ioremap_wc()"

0e12580

This reverts commit 855ac46.

Revert "FROMLIST: riscv: mmap(): use unsigned offset type in riscv_sy…

e9f6c03

…s_mmap" This reverts commit f2f09f1.

Revert "FROMLIST: PCI: sg2042: Add Sophgo SG2042 PCIe driver"

6c0062e

This reverts commit ba538ba.

Revert "FROMLIST: PCI: cadence: Check pcie-ops before using it"

affbe6a

This reverts commit d0253a4.

Revert "FROMLIST: dt-bindings: pci: Add Sophgo SG2042 PCIe host"

c86037a

This reverts commit 6060c57.

Revert "FROMLIST: dts: sophgo: sg2042: added numa id description"

542c906

This reverts commit cc98996.

MingcongBai pushed a commit that referenced this pull request Oct 12, 2025

arm64: dts: apple: t8103: Add PCI power enable GPIOs

cd6209d

t8103: - WLAN (SMC PMU GPIO #13) Signed-off-by: Hector Martin <marcan@marcan.st>

MingcongBai pushed a commit that referenced this pull request Oct 12, 2025

arm64: dts: apple: t600x: Add PCI power enable GPIOs

0571e32

- WLAN (SMC PMU GPIO #13) - SD (SMC PMU GPIO torvalds#26) Signed-off-by: Hector Martin <marcan@marcan.st>

ij-intel and others added 5 commits October 14, 2025 12:10

RevySR force-pushed the aosc/rv/v6.17.y branch from 1d7cd5d to d1cff7d Compare October 14, 2025 04:11

MingcongBai closed this Oct 14, 2025

MingcongBai mentioned this pull request Oct 14, 2025

linux-kernel-rc: update to 6.18.0-rc1 AOSC-Dev/aosc-os-abbs#13035

Merged

7 tasks

MingcongBai mentioned this pull request Oct 23, 2025

linux-kernel: update to 6.17.5 AOSC-Dev/aosc-os-abbs#13211

Open

7 tasks

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Uh oh!

rv/sg204x: update patchset #13

rv/sg204x: update patchset #13

Uh oh!

RevySR commented Oct 10, 2025

Uh oh!

MingcongBai commented Oct 14, 2025

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

8 participants

rv/sg204x: update patchset #13

rv/sg204x: update patchset #13

Uh oh!

Conversation

RevySR commented Oct 10, 2025

Uh oh!

MingcongBai commented Oct 14, 2025

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

8 participants