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feat(baremetal): Enable MMU and caches on secondary PEs#296

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chetan-rathore merged 1 commit intoARM-software:mainfrom
SapthagiriP:main
Mar 24, 2026
Merged

feat(baremetal): Enable MMU and caches on secondary PEs#296
chetan-rathore merged 1 commit intoARM-software:mainfrom
SapthagiriP:main

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  • Capture primary PE's MMU configuration during PE info table creation
  • Secondary PEs now enable MMU and caches using primary PE's configuration
  • Disable MMU and caches before PSCI CPU_OFF on secondary PEs
  • This ensures consistent memory behavior across all PEs during test execution

Change-Id: I8bd56c1f40a37f23d080de05cb7c6e2bfea57c8b

 - Capture primary PE's MMU configuration during PE info table creation
 - Secondary PEs now enable MMU and caches using primary PE's configuration
 - Disable MMU and caches before PSCI CPU_OFF on secondary PEs
 - This ensures consistent memory behavior across all PEs during test execution

Signed-off-by: sapthagiri padmanabhan <sapthagiri.padmanabhan@arm.com>
Change-Id: I8bd56c1f40a37f23d080de05cb7c6e2bfea57c8b
@chetan-rathore chetan-rathore merged commit 4ae0b4b into ARM-software:main Mar 24, 2026
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2 participants