board: mint D-PRLR-1..5 for probe-r2il-live-regfile-v1

[AdaWorldAPI]

Board-only, two files. Third in the arc: #1155 (parent plan), #1156 (the census), this.

probe-r2il-live-regfile-v1 is the second instance of the same defect — a GREEN probe (18/18, seven disable runs red-then-green) that was invisible to every discovery path because it carried no D-ids and no board rows. One of the 53 counted in #1156.

Ids are minted against sections that already exist; no scope added.

Two results worth reaching from an index rather than by reading 286 lines

D-PRLR-4 — the §7.8 facet binding is a PROJECTION, not a byte-identity. SLEIGH lays the 6502 out across 55 bytes because it models each status flag as its own byte register, while the semantic register file is 7. So a 12-byte V3 facet register holds the register file with room to spare, but never matches SLEIGH's layout. Pinned two-sided by the_sleigh_register_space_is_sparse_so_the_facet_binding_is_a_projection, which fails if SLEIGH ever packs the 6502 into 12 bytes — forcing a re-measure instead of letting a stale note stand.

D-PRLR-5 — r2sleigh's CI has never run. The workflow declares cargo test --workspace --all-features, which would execute this probe, but the repo reports total_count: 0 workflow runs, ever: it targets a self-hosted runner that was never registered. So every green in §6/§7 is a local run, and so is the r2conc crate merged in r2sleigh PR #5. The row stays OPEN — moving to a hosted runner is an operator infra call (the --all-features job compiles SLEIGH specs for every architecture), not a drive-by inside a board PR.

That second one is the same lesson tesseract-rs recorded when two tests sat red for thirteen days behind a skip-guard and a CI that never fired — found here by checking rather than by being bitten, which is the only reason it is cheap.

Supersession index regenerated last, after the board writes; no diff.

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https://claude.ai/code/session_01DCfrD5y19cvFc4AoyydXYv

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• .claude/board/INTEGRATION_PLANS.md
• .claude/board/STATUS_BOARD.md

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[chatgpt-codex-connector]

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[chatgpt-codex-connector]

Qualify the full-state parity claim

On the documented 255 × 255 case, the source plan's §6a says Ghidra leaves V=1 while the reference leaves V=0, and explains that without_v() deliberately excludes that field from the headline comparison. Calling the result “byte-identical architectural state” therefore overstates what the 18 green checks establish and can mislead readers of this index; describe parity as excluding V while noting that the product and remaining fields match.

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[chatgpt-codex-connector]

Leave the V4 projection binding unverified

When this row is used to determine whether §7.8's 12-byte V4 binding has been validated, the probe only establishes that SLEIGH's raw register layout spans 55 bytes and that the semantic register set totals 7 bytes; it does not exercise a projection between those layouts. Executing SlabState against a borrowed SLEIGH-layout slab validates the lifter/executor path, not the proposed ClassView binding, so labeling it the executable falsifier for that binding makes unfinished projection work appear covered.

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[AdaWorldAPI]

Both P2s verified against the source and fixed in f6a1a26. Both were the same defect in different places: the index entry over-claiming relative to the plan it indexes.

P2-1 (the V exclusion) — correct. The plan's §6a says exactly what you quote: Ghidra's 6502 ADC assigns the unsigned carry to the signed-overflow flag, so on 255 × 255 both sides compute 0xFE01 and agree on every other field while Ghidra leaves V=1 and a real 6502 leaves V=0. The entry now reads "on every field except V" and carries the finding rather than the summary — including that the exclusion is itself two-sided (falsifier D7: it must diverge on some pairs and agree on others), so it cannot decay into "ignore that field". Worth noting the plan's §1 has the same unqualified phrasing that §6a then corrects; my entry inherited it and made it worse by dropping the correction.

P2-2 (the projection) — correct, and the sharper of the two. The probe executes SlabState against borrowed SLEIGH-layout slabs. It never binds into a 12-byte V3 facet register; it measures the two layouts (55 bytes vs 7) and concludes a projection is required. Re-worded to "the falsifier for the EXECUTABLE HALF", with the misreading stated explicitly, and D-PRLR-4 regraded from ruled to constraint measured; the projection is not built and not validated. The plan itself says "the executable half of that claim" — my entry dropped those four words and turned a scoped claim into a general one.

One more, found while verifying rather than by you: the mint is board-only. grep -c "D-PRLR" .claude/plans/probe-r2il-live-regfile-v1.md → 0, and supersession_index.py counts D-ids by scanning .claude/plans/, so the coverage column cannot see them. #1156 named the root cause as "a plan without a D-id is unaddressable" — this PR makes the plan addressable from the board, it does not put ids in the plan. Same for D-R2IL-1..5 in #1155. Recorded as a ⚠ block rather than quietly fixed, because writing ids into plan bodies edits content both PRs declared out of scope.

Thanks — this is the first external review to land on any of today's six PRs; CodeRabbit is spend-capped and Bugbot usage-capped, so the rest merged unchecked.

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[AdaWorldAPI]

Correction to my previous comment: the fix commit is abc5c8d8, not f6a1a26. That sha does not exist — I wrote it from memory instead of reading it back, in a comment whose whole subject was two claims that failed for want of checking. Recording rather than editing it away, since it is the third instance today of the same defect the council is auditing.

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