Release Public Release v1.2.0 — CPU Tomasulo · Adriel23456/ComputerEngineeringRecap

Public Release v1.2.0 — Tomasulo Algorithm CPU Simulator

This release marks the first complete CPU architecture simulator added to Computer Science Engineering Recap (CSE Recap) since the foundational TLP simulator introduced in v1.0.0.

Version v1.2.0 introduces a fully functional, production-ready Tomasulo Algorithm CPU Simulator, representing the most architecturally complex and technically demanding module of the project to date.

This is a feature-complete milestone, not an experiment.

🚀 What's New in v1.2.0

✅ Tomasulo Algorithm CPU Simulator (Completed)

A full, end-to-end simulation of a Tomasulo out-of-order execution CPU, implemented at the component level with cycle-accurate combinational and sequential separation across all 41 pipeline components.

Key features:

Complete out-of-order execution pipeline:
- Fetch → Decode → Issue → Execute → Write-Back → Commit
Full Reorder Buffer (ROB) — 32-entry circular queue with in-order commit
Register renaming via per-register Qi tags
Common Data Bus (CDB) — dual-channel arbitration with priority scheduling
Reservation Stations — RS_IntALU0/1, RS_FPALU0, RS_IntMUL0, RS_FPMUL0 with 3-tier operand and flags resolution
Execution units:
- Integer ALU (×2) — single-cycle combinational
- Floating-Point ALU — single-cycle combinational
- Integer MUL/DIV — non-pipelined multi-cycle (4 / 16 cycles)
- FP MUL/DIV/SQRT — non-pipelined multi-cycle (4 / 16 cycles)
Load Buffers (×3) and Store Buffers (×2) with AGU address resolution
Speculative branch execution with misprediction detection and full pipeline flush
4-way set-associative I-Cache (8 sets, 64-byte lines) with background prefetch and demand-miss promotion
D-Cache with store/load arbitration and memory hazard resolution
Flags Unit with speculative NZCV tracking and 3-tier resolution
Custom assembler and binary loader
Background worker thread with async step / step-until / infinite-step / step-ms / stop control
Full graphical UI: pipeline view, compiler, RAM, I-Cache, D-Cache, registers, ROB, and data analysis panels

🧱 Architectural Highlights

Clean evaluate/clockEdge separation across all 41 components — combinational and sequential logic never mixed
Single-bus architecture: all inter-component communication flows through TomasuloBus
3-tier operand resolution in every Reservation Station:
- Tier 1: Architectural value (no rename tag)
- Tier 2: ROB forwarding (result already computed)
- Tier 3: CDB snoop (wait for broadcast)
Speculative flags tracking mirroring the same 3-tier model
Full structural, data, and control hazard coverage
Memory ordering enforced through store-complete snooping and commit-side arbitration
UI fully decoupled from simulation — rendering operates on latest synced snapshot under non-blocking mutex
Fully integrated into the main application state system

🛠️ Build & Tooling

Fully integrated into the existing CMake build system
Compiles cleanly alongside all existing simulations
No architectural regressions introduced
Maintains compatibility with:
- SFML
- ImGui (Docking)
- Existing engine, UI, and audio systems

✅ Validation

Comprehensive ISA validation suite covering:
- Integer ALU operations (including carry-dependent ADC/SBC)
- Floating-point arithmetic and conversion instructions
- Rounding modes and IEEE comparison behavior
- Memory access (LDR/STR/LDRB/STRB)
- Branch correctness across all flag states
Deterministic execution under full ISA stress testing
Verified register renaming integrity, memory consistency, and pipeline commit correctness

🎯 Purpose of This Release

Version v1.2.0 represents the most technically demanding milestone in the project's history.

This release demonstrates that the architecture established in earlier versions can:

Support full CPU micro-architecture simulation
Handle out-of-order execution with speculative state
Model cycle-accurate hardware behavior at the component level
Scale to 41 cooperating pipeline components without architectural compromise
Serve as a rigorous educational and experimentation platform for computer architecture

The Tomasulo CPU Simulator is considered complete and stable.