3.0 Local Bus Port
The AmigaPCI utilizes a flexible Local Bus Port to attach a CPU and other devices to the AmigaPCI. The AmigaPCI has no CPU on the main board. Instead, the CPU is contained on the Local Bus Card attached to this bus. This approach enables easier CPU and RAM upgrades. The AmigaPCI Local Bus Card specification enables the inclusion of AUTOCONFIG, I2C, and SPI devices on the Local Bus Card. Because the AmigaPCI fast Ram must be included on the Local Bus Card, it can be optimized for the clock speed and capabilities of the CPU device implemented. This enables an upgrade path for increased performance while minimizing resources needed on the AmigaPCI main board. A reference design can be found with the AmigaPCI project.
Specific footprint dimensions for the Local Bus Card are not defined. The engineer may make the card any size they wish, within practical limits. The physical size must not extend outside the ATX specifications from the mounting point (must not extend beyond the AmigaPCI board). It must not interfere with the ATX power and ATA connectors and must not interfere with video cards or full size PCI plug in cards. The physical connector is a DIN 41612 150 pin Eurocard connector, 3 rows by 50 columns. The female (receptacle) portion is on the AmigaPCI main board. The male (plug) portion is on the Local Bus Card. Examples of these connectors are part numbers 650405-5 (style C) and 5650911-5 (style R) from TE Connectivity AMP Connectors. In addition to the connector itself, there are two additional grounded mounting points to accommodate the Local Bus Card.
Note
When DIN connector types are mixed (for example, C and R), as they are in the AmigaPCI and Local Bus Card attachment, the connector circuit numbers will not match; for example, Position A1 of the pin connector will mate with Position A32 of the receptacle connector. To ensure proper connector orientation, ensure the silk screen markings on the PCB are strictly followed. Reference: TE Connectivity publication 114-9014.
The origin datum and component points can be seen in Image 3.1. The origin of all measurements is the upper left mounting hole (datum = 0,0). The image is looking down on top of the card. The DIN connector is attached to the back of the card.
Image 3.1. Points from Datum 0,0 for the Local Bus Card.
The signals on the Local Bus Port are broken into categories. Some are specific to the MC68040/MC68060 and others are specific to the AmigaPCI. The signal descriptions are below. The flow of data (input/output/bidriectional) are defined from the perspective of the Local Bus Card. The pinout of the port is detailed in Table 3.4.
Warning
Applying TTL logic levels (+5V) to LVTTL only signals may damage devices on the AmigaPCI main board.
GND (Ground)
This is the digital supply ground used by all digital devices in the system. Local Bus Cards may connect to ground through the connector and the mounting posts.
+5VDC
This is the digital supply for TTL and TTL-like devices, such as F, LS, or HCT logic families and the Motorola MC68040.
+3.3VDC
This is the digital supply for LVTTL devices, such as LVC logic families and the Motorola MC68060.
+3.3VSB This always on power source is located on the Local Bus slot. Especially useful for I2C devices that may be used for wake-up functions. Only used for devices that require power when the system is otherwise powered off.
+1.2VDC
This is the digital supply for low power devices of certain logic families or FPGA's, like the Lattice iCE40 series.
CDONE (Configuration Done) Output
This LVTTL signal is driven by programmable logic devices (e.g. FPGA) on the Local Bus Card. When LOW, holds the entire system in reset until such time as all programmable logic devices on the AmigaPCI system have configured. In the absence of programmable logic devices, this may be left unconnected.
_CPURST (CPU Reset) Input
This LVTTL signal is driven by the system reset logic and initiates a reset of the CPU. This signal is asserted in reponse to the push button or keyboard reset action.
_RESET (System Reset) Input
This LVTTL level signal is driven by the system reset logic and initiates a reset of all logic and I/O on the AmigaPCI and Local Bus Card, but not the CPU.
_RSTOUT (Reset Out) Output
This TTL tolerant signal is driven by the CPU to initiate a reset of all logic and I/O on the AmigaPCI and Local Bus Card, but not the CPU itself.
A(31..0) (Address Bus) Bidirectional
This bus is driven by the bus master and tristated by inactive bus masters. The Local Bus devices may drive this bus with either TTL or LVTTL level logic. However, the AmigaPCI drives this bus at TTL levels. As such, it is necessary that the Local Bus Card devices be TTL, TTL tolerant, or use level shifting to convert the incoming TTL levels to the voltage required.
_AUTOVECTOR Input
During an interrupt acknowledge cycle, indicate to the CPU to generate its own vector.
D(31..0) (Data Bus) Bidirectional
This bus is driven by the bus master for writes and the target device for reads and tristated by inactive bus masters. The Local Bus devices may drive this bus with either TTL or LVTTL level logic. However, the AmigaPCI drives this bus at TTL levels. As such, it is necessary that the Local Bus Card devices be TTL, TTL tolerant, or use level shifting to convert the incoming TTL levels to the voltage required.
_DATARDY (Data Ready) Input
During PCI driven DMA cycles, wait states may be inserted by the initiating device. When this signal is asserted low, this indicates valid data is on the bus and ready to be written to RAM.
PORT (Port Size) Input
This LVTTL signal is driven by the target device and tristated by inactive target devices. Strictly address driven. Used to indicate the data bus width of the target device. Logic low (0) indicates a 32-bit port. Logic high (1) indicates a 16-bit port.
R_W (Read/Write) Bidirectional
This TTL tolerant signal is driven by the bus master and tristated by inactive bus masters.
SIZ(1..0) (Transfer Size) Bidirectional
This TTL tolerant bus is driven by the bus master and tristated by inactive bus masters. These are the MC68040/MC68060 transfer size signals.
_TACK (Transfer Acknowledge) Bidirectional
This LVTTL signal is driven by the target device and tristated by inactive target devices. Assertion indicates that the target device has completed the data transfer process for writes or has driven the data bus with the requested data for reads. Equivalent to the MC68040/MC68060 _TA signal.
_TBI (Tranfer Burst Inhibit) Input
This LVTTL signal is driven by the target device and tristated by inactive target devices. Inhibits a burst cycle in favor of individual data transfers. Asserted with _TACK.
_TCI (Tranfer Cache Inhibit) Input
This LVTTL signal is driven by the target device and tristated by inactive target devices. Inhibits caching of data from a data transfer burst cycle. Asserted with _TACK.
_TEA (Tranfer Error Acknowledge) Input
This LVTTL signal is driven by the target device and tristated by inactive target devices. Asserted with _TACK to indicate a retry condition exists or asserted alone to indicate a cycle request cannot be completed (bus error).
TT(1..0) (Transfer Type) Bidirectional
This TTL tolerant bus is driven by the bus master and tristated by inactive bus masters. These are the MC68040/MC68060 transfer type signals.
TM(2..0) (Transfer Modifiers) Bidirectional
This TTL tolerant bus is driven by the bus master and tristated by inactive bus masters. These are the MC68040/MC68060 transfer modifier signals.
_TS (Transfer Start) Bidirectional
This TTL tolerant signal is driven by the bus master and tristated by inactive bus masters. Indicates the start of a data transfer cycle.
_BB (Bus Busy) Bidirectional
This TTL tolerant signal is driven by the bus master and tristated by inactive bus masters. Indicates the bus master is actively using the bus. This signal must not be unecessarily held asserted as that will prevent other devices from becoming bus masters.
_BG (Bus Grant) Input
This LVTTL is asserted by the bus arbitor. Assertion indicates the CPU on the Local Bus Card has control of the system bus. Unless bus lock (_LOCK) has been asserted by the bus master, _BG may be negated at any time. Negation indicates either the PCI Local Bridge has the bus (with assertion of _BB) or no device has the bus (_BB is negated). A bus master must not take control of the system bus until _BB has been negated. When no device is actively requesting the bus, _BG is asserted.
_BR (Bus Request) Output
This TTL tolerant signal is asserted by the CPU on the Local Bus Card to indicate a bus request. The CPU must not take control of the bus until it has been granted the bus by the assertion of _BG.
_LOCK (Bus Lock) Output
This TTL tolerant signal is driven exclusively by the CPU, indicating a read-modify-write cycle is in progress. When asserted, prevents the bus arbitor from granting the bus to a new device.
BCLK (Bus Clock) Output
The 40MHz LVTTL bus clock is generated on the Local Bus Card and used to synchronize data transactions between the AmigaPCI and the Local Bus device.
SCLK (SPI Clock) Input
This is the SPI clock used when reading or writing data from an SPI target device.
SDI (SPI Data In) Input
This is the data in signal of the target SPI device.
SDO (SPI Data Out) Output
This is the data out signal of the target SPI device.
_SPIAEN, _SPIBEN, _SPICEN (SPI Target Enable) Input
These are the chip select signals for target SPI devices. Each signal is independent, supporting up to three target devices on the Local Bus Card.
SDA (I2C Serial Data) Bidirectional
The I2C serial data signal is part of the I2C specification. This allows inclusion of I2C devices on the Local Bus Card.
SCL (I2C Serial Clock) Input
The I2C serial clock is part of the I2C specification. This allows inclusion of I2C devices on the Local Bus Card.
_INT2 (Amiga Interrupt 2) Output
This TTL signal is driven by a target device on the Local Bus Card. Open drain.
_INT6 (Amiga Interrupt 6) Output
This TTL signal is driven by a target device on the Local Bus Card. Open drain.
IPL(2..0) (Interrupt Level) Input
This TTL bus is driven by the Amiga chipset.
_LBCEN (Local Bus Card Enable) Input
Indicates the address on the address bus is in the $0800 0000 - $0FFF FFFF range, indicating a transaction to the Local Bus Card fast RAM space. Active low.
LBC (Reserved) Reserved.
| Column | Row A Signal | Row B Signal | Row C Signal |
|---|---|---|---|
| 1 | +5V | _AUTOVECTOR | +1.2V |
| 2 | GND | _SPICEN | _SPIBEN |
| 3 | _SPIAEN | _DATARDY | +3.3V |
| 4 | _LBCEN | RESERVED | GND |
| 5 | SCLK | SDO | SDI |
| 6 | RESERVED | GND | +5V |
| 7 | RESERVED | RESERVED | +3.3V |
| 8 | PORTSIZE | _BB | GND |
| 9 | A12 | A13 | GND |
| 10 | A14 | A0 | A15 |
| 11 | A1 | A2 | A3 |
| 12 | A4 | +3.3V | +5V |
| 13 | +1.2V | +3.3V | _INT2 |
| 14 | +5V | GND | LBC |
| 15 | A6 | A5 | A9 |
| 16 | A8 | A7 | GND |
| 17 | A11 | A10 | GND |
| 18 | _BR | _LOCK | _CPURST |
| 19 | TM0 | R_W | TM1 |
| 20 | TM2 | D28 | +3.3V |
| 21 | D26 | D24 | +3.3VSB |
| 22 | D31 | D30 | D21 |
| 23 | D29 | D27 | SIZ0 |
| 24 | SIZ1 | _TS | GND |
| 25 | D20 | D22 | GND |
| 26 | D25 | D19 | D23 |
| 27 | D17 | D15 | D14 |
| 28 | +3.3V | _TACK | _TEA |
| 29 | +5V | CDONE | _BG |
| 30 | _TBI | _INT6 | _TCI |
| 31 | GND | D18 | D13 |
| 32 | +5V | D16 | D12 |
| 33 | +5V | D11 | D10 |
| 34 | D8 | D9 | _IPL0 |
| 35 | BCLK | _RESET | _IPL1 |
| 36 | GND | _IPL2 | D7 |
| 37 | GND | D6 | D5 |
| 38 | D2 | D4 | D1 |
| 39 | D0 | D3 | TT0 |
| 40 | +5V | TT1 | SCL |
| 41 | +3.3V | SDA | _RSTOUT |
| 42 | A22 | A26 | A28 |
| 43 | A24 | A30 | A29 |
| 44 | GND | A31 | A27 |
| 45 | GND | A25 | A21 |
| 46 | A23 | A20 | A19 |
| 47 | A18 | A17 | A16 |
| 48 | +3.3V | RESERVED | RESERVED |
| 49 | +3.3V | RESERVED | GND |
| 50 | +5V | RESERVED | GND |