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AmigaPCI PCI Developers Guide
The PCI Local Bus (PCI, herein) is a processor independent, 32-bit expasion bus. The AmigaPCI specification is designed to comply with the PCI Local Bus Revision 2.3 specificiation. Each slot supports Universal and 5V cards, as defined in the PCI Local Bus Revision 2.3 specification. The PCI bridge logic translates data requests from the Motorola processor and PCI devices in order that they may communicate. This specification is compatible with Motorola MC68000 series processors. While this document is written with the Motorola MC68040 in mind, the information can be applied to other Motorola processors, such as the MC68060.
Motorola MC68000 series processors are big endian devices. PCI devices, by contrast, are little endian devices. This means the data bus must be byte swapped to provide compatability between devices with different endianness*. The AmigaPCI specification implements an address invariance system with byte swapping to achieve the endian conversion necessary for the CPU and PCI devices to communicate.
Table 1.1a. Order of byte consumption in big and little endian devices.
| Endianess | Hex Value Order of Consumption |
|---|---|
| 0x0002 0804 | |
| Big | START----> |
| Little | <----START |
The smallest unit of data considered by the PCI specification is one byte. With this consideration, data bytes are swapped to accomodate the conversion in endianess. This byte swapping is implemented in the AmigaPCI Local PCI Bridge hardware.
Table 1.1b. Byte swapping between big and little endian devices.
| Endianess | Hex Value | Address 0x00 | Address 0x01 | Address 0x02 | Address 0x03 |
|---|---|---|---|---|---|
| Big | 0x0002 0804 | 0x00 | 0x02 | 0x08 | 0x04 |
| Little | 0x0408 0200 | 0x04 | 0x08 | 0x02 | 0x00 |
*Application Note AN2285. Data Movement Between Big-Endian and Little-Endian Devices. Rev 2.2. Freescale Semiconductor. 2008
Each PCI slot has four interrupt signals, identified as _INTA, _INTB, _INTC, and _INTD. Single function PCI devices are only allowed to use _INTA. The remaining signals are used in the event of a multifunction PCI device, with one interrupt line per PCI function. As a hypothetical example, a multifunction I/O device may use _INTA for a floppy drive interface, _INTB for a hard drive interface, _INTC for a serial interface, etc. For the purposes of the AmigaPCI design, _INTA, _INTB, _INTC, and _INTD are OR'd together and connected to the Amiga's _INT2 signal. The Local PCI Bridge will continue to assert _INT2 until all PCI devices have negated their interrupt requests.
There are two read/write registers on the bridge that respond at address $9FC0 8000. The startup states of these registers are held until the appropriate register is written to with a new value.
| Register | Bit | Startup State | Set (1) | Cleared (0) |
|---|---|---|---|---|
| PCI Bus Reset | D31 | Hold PCI Devices in Reset | Devices Released from Reset | Hold PCI Devices in Reset |
| Interrupt Enable | D30 | Disable Interrupt Passthrough | Enable Interrupt Passthrough | Disable Interrupt Passthrough |
| RESERVED | D29 to D0 |
Each PCI target device may be configured by an AUTOCONFIG-like process or by software configuration. During configuration each target PCI slot is polled to obtain the capabilities and address space needs of the target device(s) present.
The host bridge base address is $8000 0000. All PCI devices may be accessed through the host bridge, which acts as an interface between devices on the CPU bus and devices on the PCI bus. The host bridge also handles bus arbitration. During each CPU data transfer cycle, the address information is broadcast by the host bridge to the PCI bus. If any devices respond by asserting _DEVSEL, the host bridge proceeds with the PCI cycle. Otherwise, the host bridge returns to an idle state.
The AmigaPCI uses the addressing scheme shown below for accessing the parallel address spaces of each PCI device. The address spaces are as follows: Memory space (broken into cachable and non-cachable), I/O space, Type 0 Config space, and Type 1 Config space. The following sections describe how to access each of these spaces on the AmigaPCI.
Table 2.2 PCI Host Bridge Memory Map
| Starting Address | Ending Address | Description |
|---|---|---|
| $8000 0000 | $9FBF FFFF | Memory Expansion Space |
| $9FC0 0000 | $9FC0 FFFF | Bridge Register Space |
| $9FC1 0000 | $9FC8 FFFF | Type 0 Configuration Space |
| $9FC9 0000 | $9FD0 FFFF | Reserved |
| $9FD1 0000 | $9FDF FFFF | Type 1 Configuration Space |
| $9FE0 0000 | $9FFF FFFF | I/O Expansion Space |
| $A000 0000 | $BFFF FFFF | Cache Line Expansion Space |
There are two memory expansion spaces available to the PCI bus. The space a device is assigned to is determined by whether the PCI device supports cache line burst transfers. When a PCI device is configured, it may be placed in either space, but not both simultaneously. The memory space assigned will dictate the PCI bus commands issued during data transfer cycles.
Memory Read and Memory Write commands are posted to the PCI bus in this space. If an attempted cache burst transfer is initiated by the CPU, the cycle will be terminated with assertion of transfer burst inhibit. Devices not supporting cache line transfers should be placed in this space.
Memory Read, Memory Write, Memory Read Line, and Memory Write and Invalidate commands are posted to the PCI bus in this space. The exact PCI bus command will be determined by the current CPU cycle type. Devices supporting cache line transfers should be placed in this space.
Two megabytes of space is available for I/O devices. In this space, only I/O read and I/O write commands are posted to the PCI bus. I/O devices are not recommended for new designs. Address bits AD[31:20] on the PCI bus are set to $0 during an I/O space access.
The Type 0 configuration space of each device on the PCI bus can be accessed by probing the correct address. The addressing scheme is described below. The data bit order shown in the tables is aligned to big endian accesses from the CPU. The host bridge automatically byte swaps the data bus in both directions. Thus, any data on the CPU side of the bridge will be in big endian order. Conversely, any data on the PCI side of the bus is in little endian order. Becuase of the byte swapping, it is critical to consider how the data will be presented when referencing tables in the PCI specifications. Address translation that may be required is implemented by the host bridge. For example, AD[1:0] must be $0 for accesses to the Type 0 Configuration space. To support this, the host bridge automatically sets AD[1:0] = $0 during this access type. In addition, AD[31:20] are set to $0.
Table 2.2.3a Type 0 Configuration Space Access.
| CPU Address Bus Bits | Description |
|---|---|
| 31:20 | Type 0 configuration space ($9FC). |
| 19:16 | Slot to Access. See Table 2.2.3b. |
| 15:11 | Reserved. Should be $0. |
| 10:8 | Value identifying the function ID of target slot. |
| 7:2 | Configuration Register Offset. |
| 1:0 | Byte start address. Defined by CPU. |
Table 2.2.3b Device Access
| A[19:16] Binary | Hex | Result |
|---|---|---|
| 0001 | $1 | PCI Slot 0 _IDSEL. |
| 0010 | $2 | PCI Slot 1 _IDSEL. |
| 0100 | $4 | PCI Slot 2 _IDSEL. |
| 1000 | $8 | PCI Slot 3 _IDSEL. |
| 0011 | $3 | PCI Slot 4 _IDSEL. |
Table 2.2.3c Access Examples
| CPU Address Bus | Target |
|---|---|
| $9FC0 8000 | Host bridge register. |
| $9FC4 0000 | Register 0x0 from PCI device 0 on slot 2. |
| $9FC3 0000 | Register 0x0 from PCI device 0 on slot 4. |
| $9FC3 000C | Register 0xC from PCI device 0 on slot 4. |
| $9FC1 0100 | Register 0x0 from PCI device 1 on slot 1. |
| $9FC1 0200 | Register 0x0 from PCI device 2 on slot 1. |
The Type 1 configuration space of each device on the PCI bus can be accessed by probing the correct address. Up to 15 additional buses can be supported using the addressing scheme described below. Bus $0 is reserved for the system host bridge. The host bridge automatically byte swaps the data bus in both directions. Thus, any data on the CPU side of the bridge will be in big endian order. Conversely, any data on the PCI side of the bus is in little endian order. Becuase of the byte swapping, it is critical to consider how the data will be presented when referencing tables in the PCI specifications. Address translation that may be required is implemented by the host bridge. For example, AD[1:0) must be $1 for accesses to the Type 1 Configuration space. To support this, the host bridge automatically sets AD[1:0] = $1 during this access type. In addition, AD[31:20] is set to $0.
Table 2.2.4a Type 1 Configuration Space Access
| CPU Address Bus | Description |
|---|---|
| 31:20 | Type 1 configuration space ($9FD). |
| 19:16 | Bus number ($1 - $F) |
| 15:11 | Target slot on the target bus. |
| 10:8 | Value identifying the function ID of target slot. |
| 7:2 | Configuration Register Offset. |
| 1:0 | Byte start address. Defined by CPU. |
PCI cards with AmigaOS ROMs will be configured via an AUTOCONFIG-like process at startup. In order to complete the configuration process, the PCI devices must inclue a ROM or psuedo-ROM to supply the necessary information. The first 64KB of ROM space is designated as the PCI Data Structure. To determine the target architecture of the ROM image, the value Code Type must be set. For AmigaOS ROM images, the Code Type at offset 0x14 must be 0x68. All other values will be ignored.
Once an AmigaOS ROM is identified, specifications such as the device manufacturer, product number, device capabilities, etc, are read from the device. AmigaOS will assign a base address to each device on the PCI card. This procedure is then repeated for each PCI device installed. Once complete, each PCI device may be accessed by the assigned base address.
Direct bus access is available to the CPU and PCI devices via bus mastering. When a device has mastered the bus, it has control of the entire AmigaPCI system and may directly access any valid address location. This is typically done for direct reading and writing of memory (DMA) or direct control of chipset or other functions. The AmigaPCI bus arbiter accepts bus requests from the CPU and each device on the PCI bus. Each slot on the PCI bus has a dedicated bus request signal. The bus arbiter implements a fairness protocol to prevent a single device from controlling the bus at the expense of other devices.
The bridge supports non-burst and burst mode transfers. The transfer method selected by the bridge is conditioned by the address space in which the target device resides. See Section 2.2. If the CPU attempts a burst transfer in the memory space reserved for non-burst devices, the cycle will be terminated after the first data transfer with a transfer burst inhibit signal. This will force the CPU to transfer the remaining data via individual transfer cycles. So, it is always preferable to configure burst-capable PCI devices in the cache line address space.
The bridge supports two modes of DMA transfers. The first is direct data transfer between the PCI device and a target device also on the PCI bus. The second is direct data transfer between the PCI device and a target device on the AmigaPCI bus. The value of the address bit on AD31 during a DMA request is used to condition the target bus of the DMA request. Since all PCI devices are configured in the space at or greater than $8000 0000, all DMA requests to the PCI bus will set address bit AD31 = 1. All devices on the AmigaPCI are at addresses less than $8000 0000. Thus, all DMA requests to the AmigaPCI will set address bit AD31 = 0.
Once a PCI device is granted exclusive access to the AmigaPCI bus, it may access any address space on the AmigaPCI. There are no limitations to which addresses will respond to data transfer requests. This would be most useful for data transfers to and from the AmigaPCI memory spaces, but also to communicate with the chipset registers.
A PCI device is granted exlusive access to the PCI bus where the target device is also on the PCI bus. Not much to say here.