Electrical & Computer Engineering student at the University of Thessaly, interested in computer architecture, FPGA design, hardware acceleration, RISC-V, and AI hardware.
I enjoy working across the hardware–software boundary, from RTL and processor microarchitecture to FPGA accelerators and performance-oriented software.
- Computer Architecture & Microarchitecture
- FPGA & Digital Design
- Hardware Accelerators
- RISC-V
- Hardware–Software Co-design
- AI Hardware
- VLSI & EDA
Single-issue out-of-order processor implemented in Verilog and deployed on a Zynq-7000 FPGA.
- Tomasulo-style dynamic scheduling
- Register renaming and reorder buffer
- Pipelined multiplication and multi-cycle division
- Load/store and branch support
- UART-based control and debugging interface
- FPGA implementation running at approximately 90 MHz
Hardware accelerator developed using Vitis HLS and deployed on a ZedBoard.
- Highly parallel processing architecture
- Loop unrolling and pipelining with II = 1
- Optimized memory bandwidth and data movement
- Evaluated against CPU SIMD and OpenMP implementations
Working on accelerating Llama2/TinyStories inference using the open-source Vortex RISC-V GPGPU architecture on AMD/Xilinx Alveo FPGA platforms.
Current work includes OpenCL kernel development for:
- QKV projection, RoPE and KV cache updates
- Attention output projection and residual connection
- SwiGLU feed-forward network
- Output projection and residual connection
Research project exploring machine-learning and graph-neural-network models for effective capacitance prediction in VLSI interconnects.
- Circuit graph representations
- GNN and MLP architectures
- SPICE-based dataset generation
- RC network feature engineering
- Timing and interconnect modeling
Complete Pong implementation in Verilog with real-time HDMI video output, including pixel generation, game logic and FPGA deployment.
Circuit simulator developed in C, implementing numerical techniques used in SPICE-style circuit simulation.
Hardware & HDL: Verilog · SystemVerilog · FPGA · RTL · HLS
Computer Architecture: RISC-V · Tomasulo · Out-of-Order Execution · GPGPU
Programming: C · C++ · Python · OpenCL · SystemC
Tools: Vivado · Vitis · Vitis HLS · Git · Linux · SPICE
Integrated MEng in Electrical & Computer Engineering University of Thessaly 2022 – 2027