MIPI CSI2 to DSI2
Quick Start Guide
Build Instructions
This Quick Start Guide describes the architecture of this reference design. It also describes the hardware and software setup needed to run it.
- Overview
- Theory of Operation
- Install the Quartus Prime Pro Programmer
- Configure the Board for the Demo
- Flash the FPGA configuration file.
- Run the Demo
This reference design demonstrates the Agilex-3 MIPI capabilities. Video from the ams OSRAM Mira220 camera enters the Agilex-3 via the MIPI CSI-2 and goes though a few Video ISP modules and gets triple-buffered in a pseudoRAM. From there is is read, passes through more Video ISP and MIPI DSI-2, on its way to the DSI LCD panel.
In addition to live video, touching the screen displays a yellow frame at the finger position. As the user moves the finger on the screen, the yellow frame tracks it.
The Mira220 is initialized to generate 1280x800 image at 30fps. MIPI camera data enters the Agilex-3 via the hard DPHY IP then enters the CSI-2 RX IP to be processed and sent out as an axi video streaming interface. It passes through White Balance and Demosaic IP to convert 12-bit Bayer to 24-bit RGB as 4 pixels in parallel. Since the pseudoRAM is 16MB and its controller is limited to 100MHz operation in evaluation mode, the video data needs to be scaled down. The scaling is done to 640x400 arbitrarily. From there the Video Frame Writer stores the frame in 3 rolling buffers (in the pseudoRAM).
On the output side, the Video Frame Reader IP reads image data from the pseudoRAM as 1 pixel in parallel, it goes through scaling up to regain the 1280x800 resolution. A mixer is used to allow the yellow frame overlay to occur, and a Test Pattern Generator for debug purposes, to be mixed in onto the displayed background image. The DSI-2 expects streaming data to be in "Full" variant, so a protocol converter IP is used to make that conversion. The DSI-2 takes the streaming video and applies user-programmed timing parameters to get a 1280x800 @60fps display on the DSI panel.
The Camera configuration file used by the Sensor Configuration Tool v1.4 is provided in the scripts subfolder. The user can modify it to obtain a different resolution. From that tool, a .csv file is exported and edited to look like the .txt file in the same folder. Initialization settings from the .txt file are used to populate the Mira220 .h file in the software/mipi_app subfolder.
In addition to setting up IP blocks in the Platform Designer tool, the user still does more initialization using a NIOS-V CPU. Selecting which video source drives the Mixer is done via user interaction by means of a terminal emulator running at 115200 baud.
The DSI timing is important and should match DSI LCD panel needs. The diagram below shows how parameter settings map into the video frame.
The timing diagrams below show how these parameters map into the video timing diagram.
The reference design includes
- Nios® V/m Microcontroller
- Onchip RAM (64KB)
- DDR4 memory
- System ID peripheral
- Mailbox Client
- MIPI DPHY/CSI2
- Video & Vision Processing IP
- Push-Button
- 2x RGB LED
- Light Weight UART
The following components are required for the demo:
- AXC3000 (TEI0131) development board,
- USB C Cable
- 2x jumper wires
- ams OSRAM Mira220 camera Kit "Mira220_RGB_mini_SB" (with lens)
- Waveshare 8" 1280x800 DSI LCD display
- Plug the USB Cable into the LCD display USB-C port
- Connect jumper wires to the LCD 5V/GND header pins
- Connect 15-pin FPC cable to the LCD panel with conductors facing up
- Connect jumper wires to the AXC3000 5V/GND MKR header pins, which provides it with 5V from the LCD panel
- Connect a 15-pin FPC to the Mira220 camera with the conductor side facing the camera PCB
- Connect the Mira220 camera to CRUVI adapter TEI0278 "Camera" connector via 15-pin FPC
- Connect the LCD Panel to the CRUVI adapter TEI0278 "Display" connector via 15-pin FPC
- Download the FPGA jic image axe5000_top.jic
Open the Quartus Programmer
$ Tools --> Programmer
Add JTAG Hardware. If the Hardware Setup has 'No hardware'
$ Press the Hardware Setup button
$ Double click USB Blaster III. Press Close
Select the A5EC008BM16A device in the topology diagram
$ Edit --> Change File. Select axe5000_top.jic
$ Click the 'Program/Configure' check box.
$ Processing --> Start
This will take up to a minute to complete.
$ Open Tera-Term or equivalent terminal program
$ set its baud rate to 115200
$ Press the S1 button to configure the FPGA
Initially, the code displays 16 different colors on the RGB LED. Once it is complete, it reads the System ID peripheral and displays it. It is then held in a while loop forever. Press S2 to invoke the Interrupt Service Routine (ISR) to change the LED color.
Release Contents
Prerequisites
Build the Reference Design
| Component | Location | Branch | Tag/Commit ID |
|---|---|---|---|
| GHRD | https://github.com/ArrowElectronics/refdes-agilex5 | master | QPDS26.1_REL_GSRD_PR/4c386a5259ca487f4fdc80e9d7c9a404b5ec39fc |
- Host machine running Windows or Linux.
- Internet connection to download the tools and clone the repositories from github. If you are behind a firewall you will need your system administrator to enable you to get to the git trees.
- Quartus Prime Pro version 26.1
- Licenses :
- NIOS-V free license
- CSI-2 and DSI-2 free licenses
- Video and Vision Processing IP evaluation License
- Synaptic Labs xSPI IP License
- Ashling RiscFree IDE for Intel FPGAs 26.1, if modifying software
For Windows: Start --> Altera 26.1.xx Pro Edition --> Nios V Command Shell.
For Linux or WSL: Open a shell and then enter niosv-shell at the prompt.
$ sudo rm -rf agilex_3
$ mkdir agilex_3
$ cd agilex_3
$ export TOP_FOLDER=`pwd`
$ cd $TOP_FOLDER
$ git clone https://github.com/ArrowElectronics/refdes-agilex3
$ cd refdes-agilex5/axc3000/csi2_dsi2_refdes
Create the User BSP
niosv-bsp \
--create \
--quartus-project=./quartus/axc3000_mipi_top.qpf \
--qsys=./quartus/top_system.qsys \
--type=hal \
--cmd="add_section_mapping .bss niosv_system_0_onchip_memory" \
--cmd="add_section_mapping .heap niosv_system_0_onchip_memory" \
--cmd="add_section_mapping .rodata niosv_system_0_onchip_memory" \
--cmd="add_section_mapping .rwdata niosv_system_0_onchip_memory" \
--cmd="add_section_mapping .stack niosv_system_0_onchip_memory" \
--cmd="add_section_mapping .text niosv_system_0_onchip_memory" \
--cmd="add_section_mapping .exceptions niosv_system_0_onchip_memory" \
./software/mipi_bsp/settings.bsp
niosv-bsp -g ./software/mipi_bsp/settings.bsp
Create the project
niosv-app \
--bsp_dir=./software/mipi_bsp \
--app_dir=./software/mipi_app \
--srcs=./software/mipi_app/niosv_mipi_mira220.c
--srcs=software/mipi_app/Mira220_1200Mbps_1280x800x30fps_inits.h
Create the project Makefile
cmake \
-G "Unix Makefiles" \
-DCMAKE_BUILD_TYPE=release \
-B software/mipi_app/build/Debug\
-S software/mipi_app
Build the project
cmake \
--build software/mipi_app/build/Debug
Compile the Quartus project
quartus_sh --flow compile axc3000_mipi_top
The following file is created:
- agilex_3/refdes-agilex3/axc3000/AXC3000_CSI2_DSI2_26.1/output_files/axc3000_mipi_top.sof
quartus_pfg \
-c output_files/axc3000_mipi_top.sof \
-o device=MT25QU256 -o flash_loader=A3CY100BM16AE7S -o mode=ASX4 \
output_files/axc3000_mipi_top.jic
The following file is created:
- agilex_3/refdes-agilex3/axc3000/AXC3000_CSI2_DSI2_26.1/output_files/axc3000_mipi_top.jic
quartus_pgm -c 1 -m jtag -o "pvbi;output_files/axc3000_mipi_top.jic@1"