MIPI CSI2 to DSI2 26.1
Quick Start Guide
Build Instructions
This Quick Start Guide describes the architecture of this reference design. It also describes the hardware and software setup needed to run it.
- Overview
- Theory of Operation
- Install the Quartus Prime Pro Programmer
- Configure the Board for the Demo
- Flash the FPGA configuration file.
- Run the Demo
This reference design demonstrates the Agilex-3 MIPI capabilities. Video from the ams OSRAM Mira220 camera enters the Agilex-3 via the MIPI DPHY/CSI-2 and goes though a few Video ISP modules and gets triple-buffered in a hyperRAM. From there it is read, passes through more Video ISP and MIPI DSI-2/DPHY, on its way to the DSI LCD panel.
In addition to live video, touching the screen displays a yellow frame at the finger position.
The Mira220 is initialized to generate 1280x800 image at 30fps, in RAW12 format over 2 data lanes running at 1200Mbps. MIPI camera data enters the Agilex-3 via the hard DPHY IP then goes thorough the CSI-2 RX IP to be processed and sent out as an axi4 video streaming interface. It passes through a minimal set of Video ISP blocks, namely the White Balance Correction IP and the Demosaic IP which converts the 12-bit Bayer to 24-bit RGB per pixel and flow as 4 pixels in parallel. The axi4 streaming data enters a Scaler IP which reduces the resolution to 640x400. From there the Video Frame Writer stores the frame in 3 rolling buffers (in the hyperRAM).
On the output side, the Video Frame Reader IP reads image data from the hyperRAM as 1 pixel in parallel, it goes through scaling up to regain the 1280x800 resolution. A mixer is used to allow the yellow frame overlay to occur, and a Test Pattern Generator for debug purposes, to be mixed in onto the displayed background image. The DSI-2 expects streaming data to be in "Full" variant, so a protocol converter IP is used to make that conversion. The DSI-2 takes the streaming video and applies user-programmed timing parameters to get a 1280x800 @60fps display on the DSI panel.
The Camera configuration file used by the Sensor Configuration Tool v1.4 is provided in the scripts subfolder. The user can modify it to obtain a different resolution. From that tool, a .csv file is exported and edited to look like the .txt file in the same folder. Initialization settings from the .txt file are used to populate the Mira220 .h file in the software/mipi_app subfolder.
In addition to setting up IP blocks in the Platform Designer tool, the user still does more initialization using a NIOS-V CPU. Selecting which video source drives the Mixer is done via user interaction by means of a terminal emulator running at 115200 baud.
The reference design includes:
- Nios® V/m Microcontroller
- Onchip RAM (96KB)
- 128Mb hyperRAM memory
- System ID peripheral
- Mailbox Client
- MIPI DPHY/CSI2
- Video & Vision Processing IP
- Push-Button
- RGB LED
- Light Weight UART
The following components are required for the demo:
- AXC3000 (TEI0131) development board
- TEI0278-01 CRUVI to MIPI adapter
- USB C Cable to power the LCD panel
- USB C Cable to configure Agilex-3 on AXC3000 board
- 2x jumper wires
- 15-pin FPC cable, 10-15 inches for Camera
- 15-pin FPC cable, 6 inches for LCD Panel
- ams OSRAM Mira220 camera Kit "Mira220_RGB_mini_SB" (with lens)
- Waveshare 8" 1280x800 DSI LCD display
- Plug the USB Cable into the LCD display USB-C port
- Connect the jumper wires to the LCD 5V and GND header pins
- Connect the 15-pin FPC cable to the LCD panel with conductors facing up
- Connect the jumper wires to the AXC3000 matching 5V and GND MKR header pins, which provides it with 5V from the LCD panel
- Connect the 15-pin FPC to the Mira220 camera with the conductor side facing the camera PCB
- Connect the Mira220 camera to the CRUVI adapter TEI0278 "Camera" connector via its 15-pin FPC
- Connect the LCD Panel to the CRUVI adapter TEI0278 "Display" connector via its 15-pin FPC
Download the FPGA jic image axc3000_mipi_top.jic
Follow the instructions in Program the JIC File
The demo runs without using a terminal for user interaction, but it is optional to perform other tasks.
$ Connect a USB-C cable between the AXC3000 board and a PC
$ Open Tera-Term or equivalent terminal program
$ Select the proper COM port
$ set its baud rate to 115200, and launch it
$ Press the S1 button to configure the FPGA from the pre-programmed QSPI
The program displays Red then Green then Blue on the RGB LED D2. These indicate the different stages of the initialization and run process. If the RGB color stops at Red or Green, then there is a problem. The terminal displays any error messages.
Pressing push-button S2 cycles through 9 steps of camera exposure settings. The exposure is set to level 6 by default.
Release Contents
Prerequisites
Build the Reference Design
| Component | Location | Branch | Tag/Commit ID |
|---|---|---|---|
| GHRD | https://github.com/ArrowElectronics/refdes-agilex3 | master | QPDS26.1_REL_AGILEX3_REFDES/d8216b8ce7b41e912fec688bc8152cdec09ceebb |
- Host machine running Windows or Linux.
- Internet connection to download the tools and clone the repositories from github. If you are behind a firewall you will need your system administrator to enable you to get to the git trees.
- Quartus Prime Pro version 26.1
- Licenses :
- NIOS-V free license
- CSI-2 and DSI-2 free licenses
- Video and Vision Processing IP evaluation License
- Synaptic Labs xSPI IP License
- Ashling RiscFree IDE for Intel FPGAs 26.1, if modifying software
For Windows: Start --> Altera 26.1.xx Pro Edition --> Nios V Command Shell.
For Linux or WSL: Open a shell and then enter niosv-shell at the prompt.
$ sudo rm -rf agilex_3
$ mkdir agilex_3
$ cd agilex_3
$ export TOP_FOLDER=`pwd`
$ cd $TOP_FOLDER
$ git clone -b QPDS26.1_REL_AGILEX3_REFDES https://github.com/ArrowElectronics/refdes-agilex3 refdes-agilex3
$ cd refdes-agilex3/axc3000/csi2_dsi2_refdes
NOTE: The "\" is not accepted by the Nios-v Command Shell because there is a <CR> character following it. The "\" is used for clarity, but a Linux bash terminal accepts it.
Create the User BSP
niosv-bsp \
--create \
--quartus-project=axc3000_mipi_top.qpf \
--qsys=top_system.qsys \
--type=hal \
--cmd="add_section_mapping .bss niosv_system_0_onchip_memory" \
--cmd="add_section_mapping .heap niosv_system_0_onchip_memory" \
--cmd="add_section_mapping .rodata niosv_system_0_onchip_memory" \
--cmd="add_section_mapping .rwdata niosv_system_0_onchip_memory" \
--cmd="add_section_mapping .stack niosv_system_0_onchip_memory" \
--cmd="add_section_mapping .text niosv_system_0_onchip_memory" \
--cmd="add_section_mapping .exceptions niosv_system_0_onchip_memory" \
./software/mipi_bsp/settings.bsp
niosv-bsp -g ./software/mipi_bsp/settings.bsp
Create the project
niosv-app \
--bsp_dir=./software/mipi_bsp \
--app_dir=./software/mipi_app \
--srcs=./software/mipi_app/niosv_mipi_mira220.c \
--srcs=./software/mipi_app/Mira220_1200Mbps_1280x800x30fps_inits.h
Create the project Makefile
cmake \
-G "Unix Makefiles" \
-DCMAKE_BUILD_TYPE=Debug\
-B software/mipi_app/build/Debug\
-S software/mipi_app
Build the project
cmake --build software/mipi_app/build/Debug
Compile the Quartus project
quartus_sh --flow compile axc3000_mipi_top
The following file is created:
- agilex_3/refdes-agilex3/axc3000/AXC3000_CSI2_DSI2_26.1/output_files/axc3000_mipi_top.sof
quartus_pfg \
-c output_files/axc3000_mipi_top.sof \
-o device=MT25QU256 -o flash_loader=A3CY100BM16AE7S -o mode=ASX4 \
output_files/axc3000_mipi_top.jic
The following file is created:
- agilex_3/refdes-agilex3/axc3000/AXC3000_CSI2_DSI2_26.1/output_files/axc3000_mipi_top.jic
Open the Quartus Programmer
$ Tools --> Programmer
Add JTAG Hardware. If the Hardware Setup has 'No hardware'
$ Press the Hardware Setup button
$ Double click USB Blaster III, then Press Close
$ Select the FPGA image and click on the **Change File...** button,
$ Navigate to the **output_files/falcon_mipi_pip.jic** file and select it
$ Check the **Program/Configure** box on the .jic row
$ Click the Start Button
