RISC‐V

RISC-V Versions & Extensions

Base ISAs

RISC-V is designed around a minimal, fixed, base ISA surrounded by optional standard extensions. The base instruction set is strictly defined by register bit-width and target environment (standard vs. reduced-register embedded). Base specifications are frozen to guarantee long-term stability and backwards compatibility.

The table below shows Zarem's support for

Version	RV32 (32-bit)	RV64 (64-bit)	RV128 (128-bit)
Standard (I)	Supported ✅	Supported ✅	Supported* ✅
Embedded (E)	Planned ⏳	Planned ⏳	N/A

* RV128 is currently not supported using Just-In-Time (JIT) emulation.

Extensions

RISC-V capabilities are extended using standardized modules, most of which are labelled simply with a letter. A standard collection of extensions (I, M, A, F, D Zifencei, and Zicsr) is collectively known as the G general purpose extension.

Extension Alias	Name / Description	Supported
I	Base Integer Instructions	Yes ✅
A	Atomic Instructions	Planned ⏳
B	Bit Manipulation (Zba_Zbb_Zbc_Zbs)	WIP ⚠️
C	Compressed Instructions (16-bit encoding)	Yes ✅
D	Double-Precision Floating-Point	Yes ✅
F	Single-Precision Floating-Point	Yes ✅
G	General-Purpose ISA (IMAFDZicsr_Zifencei)	WIP ⚠️
H	Hypervisor	Planned ⏳
J	Dynamically Translated Languages	Planned ⏳
K	Scalar Cryptography	Planned ⏳
L	Decimal Floating-Point	Planned ⏳
M	Integer Multiplication & Division	Yes ✅
N	User-Level Interrupts	Planned ⏳
P	Packed SIMD	Planned ⏳
Q	Quadruple-Precision Floating-Point	Planned ⏳
S	Supervisor Mode	Planned ⏳
T	Transactional Memory	Planned ⏳
V	Vector Operations	Planned ⏳
Zba	Bit Manipulation: Address Generation	Yes ✅
Zbb	Basic Bit Manipulation	Yes ✅
Zbc	Carry-less Multiplication	Planned ⏳
Zbs	Single-Bit Manipulation	Yes ✅
Zfh	Half-Precision Floating-Point	Planned ⏳
Zicsr	Control and Status Registers	Planned ⏳
Zifencei	Instruction-Fetch Fence	Planned ⏳

The RISC-V Register Set

RISC-V provides 32 general-purpose registers for standard profiles (or 16 registers for embedded E profiles). While all registers except x0 are architecturally identical, the RISC-V Application Binary Interface (ABI) defines standard usage conventions to ensure interoperability.

The Zero Register

• The Zero Register (zero / x0): Hardwired to always hold the value 0. Any write operations to x0 are silently discarded. It is used to synthesize instructions, (such as nop, mv, or j) and simplifies immediate comparisons and zeroing.

Return Address

• Return Address (ra): Stores the return address when executing jump-and-link instructions (jal, jalr). It is caller-saved if the function makes nested calls.

Pointer Registers

• Stack Pointer (sp): Points to the current top of the stack. By convention, the stack grows downwards (toward lower memory addresses), so a 16-byte allocation subtracts 16 from sp. Stack alignment must be maintained on 16-byte boundaries to ensure compatibility with standard calling conventions and floating-point/vector data types.
• Global Pointer (gp): Points to the middle of a 4KiB region in the static data section, allowing efficient gp-relative relaxed addressing for global variables.
• Thread Pointer (tp): Points to the thread-local storage (TLS) data structure for the currently executing thread.
• Frame Pointer (fp): Points to the start of a function's stack frame.
  • Note: Shares the physical register x8 with s0. If frame pointers are disabled by the compiler optimization flags, this register is freed up for general use as saved register s0.

Temporary vs. Saved Registers

• Temporary Registers (t0 - t6): These are caller-saved. Functions can overwrite these freely without preserving their values across calls.
• Saved Registers (s0 - s11): These are callee-saved. If a function modifies any of these registers, it must save their original values to the stack and restore them before returning.
  • Note: The s0 register s0 double-functions as the Frame Pointer (fp) when frame pointers are enabled by the compiler.

Argument and Result Register

• Argument Registers (a0 - a7): Used to pass up to 8 arguments into functions, as well as return values. Any remaining arguments are passed via the stack.
  • During an ecall (system call), a7 holds the system call number, a0 - a6 hold the syscall argumnets, and a0 holds the return value upon return.