Compositional digital ports

[ducky64]

Refactor of digital ports for compositional passives, #114. Changes DigitalSource|Sink|Bidir|Link to have an internal net port that models the physical connection. Refactors uses to try to eliminate ad-hoc .adapt_to(...) for Digital* ports in favor of using higher-level blocks that model the Digital* port directly and connect to its net.

Supporting refactors:

• Add DigitalSeriesResistor, which properly propagates digital port modeling across a series resistor.
• Add DibitalBidirSeriesResistor, which provides directioned propagation for DigitalBidir signals similar to DigitalBidirBridge semantics
• Adds a shared UsbSeriesResistor, since the pattern is shared between the nRF and RP2040 devices
• Improves doc for DigitalBidirBridge rationale
• Improved voltage modeling in the bidirectional level shifter
• Deprecates NetBlock, CircuitPortBridge, CircuitPortAdapter
• Refactors the desk controller example to use a separate UartLevelShifter block. Maybe that should be put into the core library, though it's one particular architecture of several possible.

Future TODO:

• Eliminate NetBlock, CircuitPortBridge, CircuitPortAdapter uses by refactoring the port type hierarchy

[Copilot]

Pull request overview

Refactors the digital port modeling to support compositional passives by introducing an internal .net passive port for DigitalSource/DigitalSink/DigitalBidir/DigitalLink, then updates parts and examples to connect via .net (and higher-level wrapper blocks) instead of ad-hoc .adapt_to(...) patterns. This aligns digital connectivity with the existing compositional approach used in other port families (eg, VoltageLink.net).

Changes:

• Reworks digital ports/links to be compositional (Digital* ports now contain a Passive .net, and DigitalLink connects these internal nets).
• Introduces/uses reusable series-resistor wrappers (DigitalSeriesResistor, DigitalBidirSeriesResistor, UsbSeriesResistor) and refactors multiple parts/examples to use them.
• Deprecates legacy net/adapter constructs and updates netlist-path naming and example-generated artifacts accordingly.

Reviewed changes

Copilot reviewed 95 out of 95 changed files in this pull request and generated 1 comment.

Show a summary per file

File	Description
examples/test_usb_uart.py	Replace .adapt_to(Digital*) with direct connector pin connections to modeled UART RX/TX.
examples/test_usb_source_measure.py	Replace exports/adapters with explicit DigitalBidir ports and .connected(...) mapping.
examples/test_usb_key.py	Switch from .adapt_to(DigitalBidir()) to connecting via .net on digital bundles.
examples/test_usb_fpga_programmer.py	Inline digital pin mapping through .connected(...) instead of per-pin .adapt_to(...).
examples/test_tofarray.py	Connect CAN diff signals directly via connector mapping instead of .adapt_to(...).
examples/test_swd_debugger.py	Refactor SWD connector wiring + replace discrete resistors/adapters with DigitalSeriesResistor.
examples/test_robotdriver.py	Replace exported/adapted connector pins with explicit digital ports and connected mapping.
examples/test_robotcrawler.py	Make PWM a proper DigitalSink port and map it via .connected(...).
examples/test_iot_display.py	Connect digital control via .net instead of .adapt_to(DigitalSink()).
examples/test_iot_blinds.py	Replace adapter-heavy connector exports with explicit digital ports and mapping.
examples/test_esp_programmer.py	Replace per-pin .adapt_to(...) with explicit DigitalSink ports + connector mapping.
examples/test_deskcontroller.py	Refactor Jiecang connector UART modeling and add UartLevelShifter block for architecture separation.
examples/test_blinky.py	Replace .empty() port constructions with default constructors for digital/passive ports.
examples/test_bldc_controller.py	Simplify I2C wiring through connector mapping and replace .empty() usage.
examples/UsbSourceMeasure/UsbSourceMeasure.svgpcb.js	Update edg-path comments to include internal resistor .res path.
examples/UsbSourceMeasure/UsbSourceMeasure.net	Update generated netlist component paths for internal resistor blocks.
examples/UsbFpgaProgrammer/UsbFpgaProgrammer.svgpcb.js	Update edg-path comments to internal resistor .res path.
examples/UsbFpgaProgrammer/UsbFpgaProgrammer.net	Update generated netlist component paths for internal resistor blocks.
examples/SwdDebugger/SwdDebugger.svgpcb.js	Update edg-path comments + adjust swapped resistor pad mapping consistent with refactor.
examples/SwdDebugger/SwdDebugger.net	Update generated netlist component paths + resistor pin mapping updates.
examples/Simon/Simon.svgpcb.js	Update net naming for button LED nets (generated artifact changes).
examples/Simon/Simon.net	Update corresponding generated KiCad netlist nets (generated artifact changes).
examples/PicoProbe/PicoProbe.svgpcb.js	Update edg-path comments + resistor pad mapping for USB series resistors.
examples/PicoProbe/PicoProbe.net	Update generated component origins/paths for new UsbSeriesResistor and pad mapping.
examples/Multimeter/Multimeter.svgpcb.js	Update edg-path comments + resistor pad mapping for USB series resistors.
examples/Multimeter/Multimeter.net	Update generated component origins/paths for new UsbSeriesResistor and pad mapping.
examples/IotThermalCamera/IotThermalCamera.svgpcb.js	Update edg-path comments to include internal resistor .res path.
examples/IotThermalCamera/IotThermalCamera.net	Update generated netlist component paths for internal resistor blocks.
examples/IotRollerBlinds/IotRollerBlinds.svgpcb.js	Update edg-path comments to include internal resistor .res path.
examples/IotRollerBlinds/IotRollerBlinds.net	Update generated netlist component paths for internal resistor blocks.
examples/IotLedDriver/IotLedDriver.svgpcb.js	Update edg-path comments to include internal resistor .res path.
examples/IotLedDriver/IotLedDriver.net	Update generated netlist component paths for internal resistor blocks.
examples/IotIron/IotIron.svgpcb.js	Update edg-path comments to include internal resistor .res path.
examples/IotIron/IotIron.net	Update generated netlist component paths for internal resistor blocks.
examples/IotFan/IotFan.svgpcb.js	Update edg-path comments to include internal resistor .res path.
examples/IotFan/IotFan.net	Update generated netlist component paths for internal resistor blocks.
examples/IotDisplay/IotDisplay.svgpcb.js	Update edg-path comments + fix netlist ordering of gdr net (generated artifact).
examples/IotDisplay/IotDisplay.net	Update corresponding generated KiCad netlist nets and resistor paths.
examples/IotCurtainCrawler/IotCurtainCrawler.svgpcb.js	Update edg-path comments to include internal resistor .res path.
examples/IotCurtainCrawler/IotCurtainCrawler.net	Update generated netlist component paths for internal resistor blocks.
examples/Fcml/Fcml.svgpcb.js	Update edg-path comments + resistor pad mapping for USB series resistors / bitbang network.
examples/Fcml/Fcml.net	Update generated component paths + resistor pin mapping for bitbang + USB series resistors.
examples/EspLora/EspLora.svgpcb.js	Update edg-path comments to include internal resistor .res path.
examples/EspLora/EspLora.net	Update generated netlist component paths for internal resistor blocks.
examples/DeskController/DeskController.svgpcb.js	Update generated placement/net mapping reflecting new UartLevelShifter structure.
examples/DeskController/DeskController.net	Update generated netlist paths/nets reflecting new connector + shifter hierarchy.
examples/Datalogger/Datalogger.svgpcb.js	Update netlist ordering for gdr net (generated artifact).
examples/Datalogger/Datalogger.net	Update corresponding generated KiCad netlist nets.
examples/CanAdapter/CanAdapter.svgpcb.js	Update edg-path comments to include internal resistor .res path.
examples/CanAdapter/CanAdapter.net	Update generated netlist component paths for internal resistor blocks.
edg/parts/UsbInterface_Ft232h.py	Replace hand-rolled resistor + .adapt_to(...) with DigitalSeriesResistor wrapper.
edg/parts/SwitchMatrix.py	Rewrite switch-matrix generation to connect via .net and aggregate row modeling params.
edg/parts/Rf_Sx1262.py	Model ctrl as a DigitalSink.from_supply(...) and use DigitalSeriesResistor for the recommended series resistor.
edg/parts/Oled_Er_Oled_096_1c.py	Replace connector-pin exports/adapters with explicit modeled ports and connector .connected(...) mapping.
edg/parts/Oled_Er_Oled_096_1_1.py	Same: explicit ports for passives and digital signals + connector mapping.
edg/parts/Oled_Er_Oled_091_3.py	Define SPI/digital models up front and connect via connector mapping (removes .adapt_to(...) wiring).
edg/parts/Oled_Er_Oled_028.py	Switch to modeled SPI/digital ports + connector mapping + passive pin ports.
edg/parts/Oled_Er_Oled_022.py	Convert pin exports/adapters to explicit digital ports and connector mapping.
edg/parts/Microcontroller_nRF52840.py	Remove custom USB series resistor block; use shared UsbSeriesResistor.
edg/parts/Microcontroller_Stm32f103.py	Update USB pull-up wiring to connect via .net and remove now-unneeded dm init hack.
edg/parts/Microcontroller_Rp2040.py	Remove custom RP2040 USB support block; use shared UsbSeriesResistor.
edg/parts/Microcontroller_Esp.py	Refactor programmer header wiring to direct connector mapping; initialize UART/reset signals as ports.
edg/parts/LedMatrix.py	Replace .adapt_to(...) with explicit DigitalSink element and connect via .net.
edg/parts/Lcd_Qt096t_if09.py	Convert connector exports/adapters to explicit modeled SPI/digital ports + mapping.
edg/parts/Lcd_Er_Tft1_28_3.py	Convert to explicit modeled ports (SPI/I2C/touch) + connector mapping.
edg/parts/Lcd_Ch280qv10_Ct.py	Convert many exported/adapted pins to explicit modeled ports and connect via mapping.
edg/parts/Jacdac.py	Refactor Jacdac signal path to connect via .net and build JacdacDataPort model from the incoming signal.
edg/parts/Fpga_Ice40up.py	Simplify header wiring via .connected(...) mapping (removes per-pin .adapt_to(...)).
edg/parts/EInk_WaveshareDriver.py	Convert to explicit digital/SPI ports + connector mapping; model gdr as a DigitalSource.
edg/parts/EInk_Er_Epd027_2.py	Same as above for a specific EPD panel part.
edg/parts/DebugHeaders.py	Refactor SWD header wiring to direct mapping; update reset modeling comment and add legacy warning text.
edg/parts/Connectors.py	Replace per-pin .adapt_to(...) with direct connector mapping for I2C.
edg/parts/Camera_Ov2640_Fpc24.py	Replace per-pin .adapt_to(...) with explicit ports + connector mapping; clean up Y[0..9] handling.
edg/parts/BuckConverter_TexasInstruments.py	Replace enable pull-up modeling with an explicit forced-voltage clamp + PullupResistor.
edg/electronics_model/test_bundle_netlist.py	Update expected netlist port paths to include the new internal "net" port segment.
edg/electronics_model/VoltagePorts.py	Replace adapter-based connection with explicit DigitalSource port + .net connection for the adapter.
edg/electronics_model/PassivePort.py	Migrate passive→digital adapters to PortAdapter and explicitly connect src to dst.net.
edg/electronics_model/GroundPort.py	Replace adapter-based digital-source wiring with explicit DigitalSource + .net connection.
edg/electronics_model/DigitalPorts.py	Core refactor: digital ports become compositional with .net; DigitalLink connects internal nets; bridges/adapters updated accordingly.
edg/electronics_model/CircuitBlock.py	Deprecate NetBlock, CircuitPortBridge, CircuitPortAdapter, CircuitLink with guidance toward compositional nets.
edg/abstract_parts/init.py	Export new series resistor helpers (DigitalSeriesResistor, DigitalBidirSeriesResistor, UsbSeriesResistor).
edg/abstract_parts/UsbBitBang.py	Replace ad-hoc resistor/adaptation network with the new series resistor wrapper blocks; deprecate helper.
edg/abstract_parts/PassiveFilters.py	Refactor digital RC blocks to connect via .net and make port models explicit.
edg/abstract_parts/MergedBlocks.py	Remove NetBlock inheritance and explicitly connect merged digital nets via .net.
edg/abstract_parts/LevelShifter.py	Tighten LV-side voltage/threshold modeling in bidirectional level shifter generation.
edg/abstract_parts/DummyDevices.py	Remove NetBlock inheritance and explicitly connect .net pass-through.
edg/abstract_parts/DigitalAmplifiers.py	Switch to compositional digital output wiring via .net.
edg/abstract_parts/AbstractTvsDiode.py	Convert digital TVS modeling to assign voltage limits + connect via .net.
edg/abstract_parts/AbstractTestPoint.py	Refactor digital testpoint to connect via .net.
edg/abstract_parts/AbstractSwitch.py	Refactor switch wrappers to use .net and initialize modeled ports explicitly.
edg/abstract_parts/AbstractSolidStateRelay.py	Refactor signal LED drive modeling to use .net and explicit current-draw assignments.
edg/abstract_parts/AbstractResistor.py	Add DigitalSeriesResistor, DigitalBidirSeriesResistor, UsbSeriesResistor; refactor existing pull resistors to connect via .net.
edg/abstract_parts/AbstractLed.py	Refactor LED current-draw modeling to use .net connections and explicit assignments.
edg/abstract_parts/AbstractJumper.py	Refactor digital jumper to model ports explicitly and connect via .net.
edg/abstract_parts/AbstractCapacitor.py	Refactor “digital capacitor to ground” to connect via .net instead of .adapt_to(...).

---

💡 Add Copilot custom instructions for smarter, more guided reviews. Learn how to get started.

[Copilot]

Port.empty() clears parameter initializers, which makes these ports effectively unconstrained and can mask ERC issues (eg, link voltage/threshold checks becoming too permissive via hull/intersection). Since this is a concrete level-shifter block (not a generator/forward-declare use case), prefer initializing these as VoltageSink() / UartPort() (or explicitly modeled ports) instead of .empty() so connectivity preserves meaningful digital/voltage constraints.