RISC-V simulator with Python.
- Single Stage Core
conda env create -n risc-v -f requirements.txt
conda activate risc-v
pip install -r requirements.txt
python ./code/main.py
This will automatically create an output folder called output_bk3170.
python ./code/main.py --iodir=/path/to/input/folder/
When debug is activated, the output folder will be output_bk3170_debug instead of output_bk3170.
python ./code/main.py --debug