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1. rv32i-dsp rv32i-dsp Public

   A custom RISC-V (RV32I) processor implemented in SystemVerilog, extended with a hardware DSP coprocessor, targeting the Digilent Basys 3 (Xilinx Artix-7) FPGA.

2. ECE552-5-Stage-Pipelined-Processor ECE552-5-Stage-Pipelined-Processor Public

   Forked from CullenKrasselt/ECE552-5-Stage-Pipelined-Processor

   ECE 552 - 5 Stage pipelined processor with forwarding, branch prediction and I/D caches

   Verilog

3. ECE554-Capstone-Project ECE554-Capstone-Project Public

   Forked from Samcooper01/ECE554-Capstone-Project

   FPGA based real time object tracking system

   Verilog

4. ECE755_SP25_Project ECE755_SP25_Project Public

   Forked from CullenKrasselt/ECE755_SP25_Project

   Verilog