v1.0.4
Zerobase v1.0.4
The documentation for Zerobase v1.0.4 is available at https://zerobase.chipstack.vn. This release focuses on major flash memory optimizations and introduces support for the new Zerobase Core board.
Breaking Changes Since Release v1.0.3
- LTO (Link Time Optimization): Enabled aggressive flash memory optimization that may affect some edge-case compatibility.
1. Feature
- Added Zerobase Core board support: New compact board variant with optimized pin layout.
- LTO Flash Memory Optimization: Implemented Link Time Optimization across all libraries and core functions.
- Enhanced compiler optimizations for reduced binary size across all board variants.
1.1 New Board: Zerobase Core
The Zerobase Core is a new compact board variant designed for space-constrained applications:
Key Features:
- Compact form factor: Smaller footprint while maintaining essential functionality
- Optimized pin layout: Streamlined pin arrangement for easier prototyping
- Cost-effective: Reduced component count for budget-conscious projects
- Full compatibility: Supports all existing Zerobase libraries and examples
- Same CH32V microcontroller: Maintains performance and feature parity
Pin Configuration:
- Essential GPIO pins maintained
- Standard communication interfaces (UART, I2C, SPI)
- Analog input capabilities preserved
- USB programming interface included
2. Flash Memory Optimization Results
2.1 Zerobase 2 Performance Improvements
Comprehensive testing shows significant flash memory reduction across all functions:
| Function | Before LTO | After LTO | Improvement |
|---|---|---|---|
| Digital I/O (LED/Button) | 11% | 9% | 2% reduction |
| Analog I/O | 16% | 12% | 4% reduction |
| Serial Communication | 43% | 35% | 8% reduction |
| UART (Serial1/2/3) | 14% | 12% | 2% reduction |
| Buzzer (Tone) | 15% | 13% | 2% reduction |
| Ultrasonic (pulseIn) | 45% | 38% | 7% reduction |
| Stepper Motor | 14% | 12% | 2% reduction |
| IR Remote Decoder | 42% | 35% | 7% reduction |
| I2C LCD Display | 22% | 18% | 4% reduction |
| I2C ADC + LCD | 22% | 17% | 5% reduction |
| RTC + LCD | 23% | 19% | 4% reduction |
| OLED Display | 35% | 31% | 4% reduction |
| Internal EEPROM | 22% | 18% | 4% reduction |
| External EEPROM | 51% | 42% | 9% reduction |
| OneWire Temperature | 38% | 32% | 6% reduction |
| SPI RFID Reader | 49% | 41% | 8% reduction |
| CAN Communication | 57% | 46% | 11% reduction |
2.2 Zerobase Performance Improvements
Even more dramatic improvements for the original Zerobase:
| Function | Before LTO | After LTO | Improvement |
|---|---|---|---|
| Digital I/O (LED/Button) | 23% | 13% | 10% reduction |
| Analog I/O | 47% | 29% | 18% reduction |
| Timing Functions | 34% | 24% | 10% reduction |
| Serial1 Communication | 49% | 37% | 12% reduction |
| Buzzer (Tone) | 42% | 33% | 9% reduction |
| Ultrasonic (pulseIn) | 48% | 28% | 20% reduction |
| Stepper Motor | 38% | 31% | 7% reduction |
| IR Remote Decoder | 49% | 39% | 10% reduction |
| I2C LCD Display | 59% | 47% | 12% reduction |
| I2C ADC + LCD | 62% | 46% | 16% reduction |
| RTC + LCD | 66% | 52% | 14% reduction |
| OLED ASCII Display | 56% | 45% | 11% reduction |
| Internal EEPROM | 56% | 47% | 9% reduction |
| External EEPROM | 57% | 43% | 14% reduction |
| OneWire Temperature | 78% | 67% | 11% reduction |
| SPI RFID Reader | 73% | 61% | 12% reduction |
3. Bugfix
- Fixed compatibility issues with LTO optimization for certain library combinations.
- Resolved flash memory allocation conflicts in complex projects.
4. Optimization
- Major flash memory reduction: Up to 20% flash savings on common functions.
- LTO implementation: Aggressive dead code elimination and function inlining.
- Library optimization: Reduced overhead in all core libraries.
Performance Summary
- Average flash reduction on Zerobase 2: 5.2% across all tested functions
- Average flash reduction on Zerobase: 12.4% across all tested functions
- Maximum flash savings: Up to 20% on complex sensor applications
- All 38 test functions: Verified working with optimizations enabled
This release significantly improves flash memory efficiency while maintaining full compatibility with existing code and introducing support for the new Zerobase Core board variant.