feat(npu): enable multi-card ParallelWrapper on Ascend - #11
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1. Add NPU 950 platform abstraction layer with device registry and auto_detect_device 2. Support mindiesd_attention and mindiesd_compile with capability detection and compile_backend 3. Adapt Qwen-Image model to use platform compile kwargs and NPU attention backend
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Adapt ParallelWrapper for multi-card Ascend (HCCL/FSDP), route long-context attention through SeqAllToAll + MindIE, and align config.device at parallel load entry while workers bind rank-local devices. Co-authored-by: Cursor <cursoragent@cursor.com>
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Combine addcmul gated residual/modulate micro-opts with MindIE-SD RMSNorm/RoPE fuse and layernorm_scale_shift under USE_MINDIESD_FUSE. Co-authored-by: Cursor <cursoragent@cursor.com>
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Add platforms abstraction with Ascend capability probes, extend utils/platform for npu/hccl/compile kwargs, and register a MindIE attention backend so PR #11 commit1 behavior can land on v1 layout. Co-authored-by: Cursor <cursoragent@cursor.com>
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Port PR #11 commit3 micro-opts onto v1 transformer_qwenimage and MindIE attention kwargs; MindIE RoPE/LN fuse gated by USE_MINDIESD_FUSE. Co-authored-by: Cursor <cursoragent@cursor.com>
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Summary
utils/platform.py(is_npu_available, HCCL backend, set/sync/empty_cache).ParallelWrapper/_worker_loopwith an NPU+HCCL path for multi-card Ulysses SP via built-inmp.spawn.device_type="npu"is explicit).Test plan
parallelism>1path still uses CUDA/NCCL (no behavior change).ASCEND_RT_VISIBLE_DEVICES=0,1,2,3withparallelism=4, sp_ulysses_degree=4, sp_ring_degree=1.device="cuda"is rewritten tonpu:{rank}inside NPU workers only.Made with Cursor