v1.2.0 — Generic rules, sentinel CI

A Generic rule set for boards designed before the fab is chosen, JLCPCB values brought to the current page, and CI that can no longer pass on a discarded rules file.

Generic rules

Generic/ holds one rule set that satisfies both JLCPCB and PCBWay: the larger of the two minimums, the smaller of the two maximums, and every rule either fab needs. It is derived in code from the two fab TOMLs, so it follows every capability update with no third file to keep in step. Each file's header lists which fab set each value. Four variants, same names as the fab folders. Asked for by @ryandesign.

JLCPCB values

• Six values updated to the current capabilities page, contributed by @jacobmarble: PTH hole 0.15mm, castellated hole 0.5mm, routed edge clearance 0.2mm, and on multilayer boards drill and via holes at 0.15mm and plated slot width at 0.35mm.
• 2-layer drill and via hole minimums corrected to 0.15mm. The old 0.3mm was JLCPCB's 1-layer figure.
• New rule: SMD pad size, a hard floor of 0.125mm on either dimension. JLCPCB's 0.25mm x 0.25mm is a recommendation and is documented rather than enforced, so fine-pitch parts stay quiet. Raised by @silbe.
• The via-hole-to-pad-hole rule is now named as inferred, since neither fab documents that pair.
• The castellated hole rule lost a (layer outer) clause that KiCad ignores on hole sizes.

CI

Every one of the twelve rule files now gets a DRC run, not just the two defaults. A sentinel rule is appended to each file under test and must fire; if KiCad silently discarded the file, the job fails. The first run caught the empty PCBWay test board (#14).

Test boards

The boards are now KiCad 9 format and need KiCad 9 or later to edit. The rules themselves still work on KiCad 8, 9 and 10. JLCPCB/TESTBOARD.md documents which object on the board exercises each rule and which rules have no object yet.

The PCBWay board is a copy of the JLCPCB board for now, so PCBWay's rules run against real objects. Tuning its pass/fail objects to PCBWay's values is tracked in #14.

Compatibility

Rules unchanged for KiCad 8, 9 and 10. Copy the file matching your order as before. Existing JLCPCB users see the value changes listed above; the multilayer defaults are tighter than before because the page is.

Tests went from 108 to 209.

Credits

Values by @jacobmarble. Generic rules idea by @ryandesign. SMD pad research and the hole-spacing question by @silbe.

v1.1.0 — generated rule matrix

The generated rule matrix, plus JLCPCB brought up to the fab's current published limits.

Rule files are now generated

Rules are no longer maintained by hand. Each fab has a TOML source of truth in capabilities/ — every value, per-variant overrides, and feature flags — and tools/generate_dru.py emits one .kicad_dru per variant:

Fab	Variants
JLCPCB	2L-1oz, 4L-1oz (default), 4L-2oz, 6L-1oz
PCBWay	2L-1oz, 4L-1oz (default), 4L-2oz, 6L-1oz

The default variant keeps the plain <FAB>.kicad_dru name, so existing instructions still work. The "choose between / uncomment" comment blocks are gone — pick the file that matches your order instead. COMPARISON.md shows every value across all variants, and DESIGN.md explains the layout.

Every generated file also carries impedance-controlled net classes (50R, 60R_Diff, 90R_Diff, 100R_Diff, 120R_Diff) using (opt …) so they guide the router without nuisance DRC errors. The values are starting points for the fab's default stackup — verify against the fab's impedance calculator for your order.

JLCPCB values updated to the 2026-08-07 capabilities page

Contributed by @silbe, verified value-by-value against the source:

• Annular rings corrected. The old PTH figure (0.075mm) was a radius-versus-diameter misreading and had been wrong since it was written. Now 0.15mm on multilayer / 0.18mm on 2-layer / 0.254mm on 2oz, per variant. NPTH is 0.45mm, via 0.05mm.
• Hole-to-hole restructured: via-to-via 0.2mm, pad-to-pad 0.45mm, and an explicit via-hole-to-pad-hole rule so the mixed case is never unconstrained.
• Clearances updated: SMD pad-to-pad 0.15mm, via/PTH/NPTH-to-track 0.2/0.28/0.2mm, plus a new inner-layer PTH clearance at 0.3mm.
• Trace width/spacing per copper weight, including new heavy-copper 2-layer figures (2.5oz/3.5oz/4.5oz).
• New rules: a guard against small-via sizes that add cost, and a plated-slot length-to-width assertion.

The toolchain now fails loudly

A review found that one-character typos in the TOML could silently disable every rule — KiCad discards a rule file containing a unit-less dimension, and kicad-cli reports that as a clean run. All closed:

• Every dimensional value is validated (positive, mm suffix) before it can reach a rule file.
• layers is required per variant — a typo can no longer generate a 4-layer file without its inner-layer rules.
• Unknown keys are rejected everywhere, so a misspelled override cannot silently fall back to the value it meant to replace.
• The orphan scan is repo-wide: a deleted or renamed fab TOML cannot leave stale rules published behind a green check.
• Rule order is handled by the generator where it matters — KiCad applies the last matching rule, so specific rules are emitted after the catch-alls that would otherwise override them.

The tool test suite grew from 23 to 108 checks in the process.

Compatibility

KiCad 8, 9 and 10, unchanged. Copy the variant file matching your order into your project as before. If you were using the default JLCPCB.kicad_dru, values have moved to the fab's current absolute minimums — the recommended figures are in COMPARISON.md if you want more margin.

Credits

JLCPCB capability updates and two excellent bug reports by @silbe. Original silkscreen report by @wailay.

v1.0.0 — first standalone release

First release as a standalone project.

These are KiCad custom design rules (.kicad_dru) matching the manufacturing capabilities of JLCPCB and PCBWay. Each fab has a rule file and a paired test board, so every rule has at least one footprint that passes or fails as expected.

Works on KiCad 8, 9 and 10 — the syntax is authored against 8 and every token used is unchanged in 9 and 10.

Getting started

Copy the .kicad_dru from JLCPCB/ or PCBWay/ into your project folder, rename it to match your project, and KiCad picks it up. Check Board Setup > Design Rules > Custom Rules for errors, then run DRC with F8.

What's in this release

Silkscreen rules actually work on real-world boards. The rules previously referenced ?.Silkscreen, which is the Board Setup display name. That name is editable, board importers (Altium, Eagle, EasyEDA, CADSTAR) overwrite it with the source tool's naming, and any board file older than KiCad 6 loads with the file-format name showing instead. On those boards the name failed to resolve — and KiCad's response is to discard the entire rule file, so every rule silently stopped being enforced, not just the silkscreen ones. All layer references now use the file-format names (F.SilkS), which nothing can rename.

This was reported by @wailay and independently upstream by @Muriukidavid. Reproduced and verified against real DRC runs on KiCad 9.0.6 and 10.0.5.

A second, quieter instance of the same fault, fixed. The Pad to Silkscreen rules tested the layer name inside the rule condition, where an unresolvable name raises no error anywhere — it just evaluates false forever. That rule had been silently dead on affected boards with nothing to indicate it.

The linter now catches this class of bug. tools/lint_dru.py validates every layer name in (layer ...) clauses, .Layer comparisons and existsOnLayer() calls, handling the ?/* wildcards and the outer/inner keywords. Display-name spellings get a message naming the correct form; unknown layers are rejected. This matters because kicad-cli pcb drc reports a rejected rule file as a clean run with exit code 0 — a green DRC in CI does not prove your custom rules ran.

Documentation for the trap, in the README's Layer names section, plus a ROADMAP.md covering what has shipped, what is next, and the project's non-goals.

Also included

Rules for both fabs covering track width and clearance, drill sizes, annular ring, via types (blind, buried and micro vias rejected), edge clearance, silkscreen text, solder-mask slivers and BGA pad-to-trace clearance. CI lints every rule file on push.

Coming next

A generated rule matrix driven by per-fab TOML — four variants per fab (2L-1oz, 4L-1oz, 4L-2oz, 6L-1oz) plus impedance-controlled net classes. In review as #1.

Credits

Originally forked from labtroll/KiCad-DesignRules by Morten Hattesen. The full commit history is preserved here, original work included.

A note on where this came from

This project previously lived at Cimos/KiCad-CustomDesignRules as a fork. GitHub excludes forks from repository search, so people looking for KiCad design rules kept landing on the inactive upstream rather than the maintained version. The old repository stays up and points here.