Update os-lib to 0.7.2#24
Merged
Merged
Conversation
soronpo
added a commit
that referenced
this pull request
Apr 1, 2026
…its init, syntax pitfalls Address 15 knowledge gap tickets from learner agents translating Verilog to DFHDL. Grouped by pattern rather than individual ticket: Type system (type-system/index.md): - Add UInt<->SInt<->Bits type conversion table and examples - Document shift operator semantics (>> is type-aware: logical for UInt, arithmetic for SInt) - Clarify UInt range slice returns UInt (not Bits), usable directly as Bits index - Add | vs || guidance for Bit values (bitwise vs logical) - Add Bits init warning: all(0) required, plain integer 0 rejected - Clarify UInt.until(1) is invalid, UInt.to mapping to $clog2 - Note subtraction LHS-must-be-wider constraint From-Verilog guide (transitioning/from-verilog/index.md): - Shift operators (no >>> in DFHDL) - UInt/SInt conversion via .bits.sint/.bits.uint - Bitwise | vs logical || for Bit assignments - Scala reserved keyword backtick escaping for port names - Bits initialization patterns (all(0), not integer 0) - Inline if-expression requires parentheses in process blocks - Unsigned literal minus signed expression restructuring - Parametric Bits constants workaround (Int CONST + .bits) - $clog2 mapping to .until/.to with edge cases - Enum match generates unique case: sparse enum gotcha Closes #10 #11 #12 #13 #14 #15 #16 #17 #18 #20 #21 #22 #23 #24 Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
soronpo
added a commit
that referenced
this pull request
Apr 3, 2026
…licing, inline-if parentheses Addresses knowledge gaps reported by learner agents: - Parametric-width Bits constants: use Bits[Int] <> CONST (closes #15, #20) - Dynamic bit indexing: .truncate for wider-than-needed index (closes #12) - Int <> CONST .bits(hi, lo) slicing note (closes #24) - Inline if parenthesization with := and <> examples (closes #21) Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Updates com.lihaoyi:os-lib from 0.7.1 to 0.7.2.
I'll automatically update this PR to resolve conflicts as long as you don't change it yourself.
If you'd like to skip this version, you can just close this PR. If you have any feedback, just mention me in the comments below.
Configure Scala Steward for your repository with a
.scala-steward.conffile.Have a fantastic day writing Scala!
Ignore future updates
Add this to your
.scala-steward.conffile to ignore future updates of this dependency:labels: library-update, semver-patch