Skip to content
View DanielCazacu25's full-sized avatar
1 follower · 0 following

Block or report DanielCazacu25

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
DanielCazacu25/README.md

Hi there! 👋 I am an Electronics Engineering student with a solid foundation in digital design, now focused on Design Verification. I build constrained-random, class-based verification environments in SystemVerilog, and I'm currently expanding into UVM.

Verilog SystemVerilog UVM Python C++ Git

🔭 I'm currently working on: Class-based and UVM verification environments for digital designs (RAM, FIFO, ALU), including reference models, scoreboards, functional coverage, and testbench validation through mutation testing.

👯 I'm looking to collaborate on: Open-source verification IP, reusable UVM components, or ASIC/FPGA design and verification projects.

🤝 I'm looking for help with: Advanced UVM architecture (register layer, virtual sequencers) and SystemVerilog Assertions.

🌱 I'm currently learning: UVM and SystemVerilog Assertions, building toward multi-environment verification projects with several DUTs under one testbench.

💬 Ask me about: Testbench architecture, functional coverage, debugging clocking-block/timing issues in SystemVerilog, or Python automation scripts for EDA tools.

⚡ Fun fact: I can spend days debugging a clocking problem only to find out it can be fixed with $isunknown

Pinned Loading

  1. Advanced-RAM-Testbench-using-SystemVerilog Advanced-RAM-Testbench-using-SystemVerilog Public

    SystemVerilog

  2. ALU ALU Public

    Verilog

  3. Elevator-FSM-Verilog Elevator-FSM-Verilog Public

    Verilog

  4. UVM_based_ALU_testbench UVM_based_ALU_testbench Public

    Verilog

  5. UVM_Based_Async_FIFO_Testbench UVM_Based_Async_FIFO_Testbench Public

    SystemVerilog

  6. True_Dual_Port_RAM True_Dual_Port_RAM Public

    Verilog