In this section you will find the work I did for my ECE 3300 (Verilog programming) @ Cal Poly Pomona.
This class consisted on using our Nexsys A7 100T to program multiple tasks you will be able to find in the different folders. Each folder will represent a different lab/task.
The files with the .v will be the code that will allow us to flash our designed task to a bitstream that will later on be shipped to the Nexsys board. The files with _tb will be testbenches files that I utilized to test before-hand the code and verify it was working as intended.