Architecture Overview

🖥️ The DRISC-V Architecture

This chapter provides detailed information about the implementation of the DRISC-V architecture. Some technical aspects may not be fully described here and are instead referenced in the RISC-V Ratified ISA Specification.

This documentation focuses on how specific components of the architecture have been implemented and how they interact with the I/O devices developed for this project.

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📑 Summary

1. Overview

• 1.1 Introduction
  General context and goals of the DRISC-V design.

• 1.2 RISC-V Implementation

  • 1.2.1 Available Instruction Set
    Instructions supported from the RISC-V specification.
  • 1.2.2 Available Non-ISA Features
    Additional architectural features not ISA Related.

2. Main Internal Components

• 2.1 ALU
  Performs mathematical operations.

• 2.2 Register File
  The internal memory of the processor.

• 2.3 Program Counter
  An special register that keeps track of the current instruction address

• 2.4 Input Buffer
  Handles incoming data from Input and Output devices.

• 2.5 RAM
  Stores data and instructions for the processor.

• 2.6 Operation Controller
  Coordinates control signals and instruction decoding.

• 2.7 CSR Controller
  Manages special purpose registers.

3. I/O Devices

3.1 Input Devices

• 3.1.1 Keyboard
  Provides typing input.

• 3.1.2 Switches and Joystick
  Provides binary and directional input.

• 3.1.3 Random Number Generator
  Provides pseudo-random values.

• 3.1.4 Real-Time Device
  Provides time-based data for scheduling or delays.

3.2 Output Devices

• 3.2.1 Screen
  Displays graphical output.

• 3.2.2 Terminal
  Displays text information.

• 3.2.3 Software Interrupt Register
  Triggers software-based interrupts for control flow.

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