RISC‐V Implementation

The RISC-V specification defines an open standard instruction set architecture (ISA) designed for modern computing systems. Unlike proprietary ISAs, RISC-V is free to use, extend, and implement, making it ideal for academic research, industrial development, and educational projects.

RISC-V follows the principles of Reduced Instruction Set Computing (RISC), emphasizing simplicity, modularity, and efficiency. Its base ISA provides a minimal set of instructions, while optional extensions—such as integer multiplication (M), control and status registers (Zicsr), and others—allow designers to tailor implementations to specific needs.

The specification is maintained by the RISC-V International organization and includes formal definitions for:

• Instruction formats and encoding
• Register usage
• Privileged and unprivileged operations
• Optional extensions for performance, security, and compatibility

In the context of the DRISC-V architecture, only a subset of the RISC-V specification is implemented, focusing on educational clarity while maintaining compatibility with standard tooling.

Beyond the core ISA, the following chapters are organized into two main categories: ISA specifications and non-ISA specifications. The ISA chapter focus on the instruction set architecture itself, covering both unprivileged and privileged operations, as well as the extensions used. Meanwhile, the non-ISA chapters focus on official RISC-V specifications that is not direcly related to the available instruction set but are still relevant for other aspects of the project.

For a complete list of all ratified and in-progress specifications—including both ISA and non-ISA documents—refer to the RISC-V Technical Specifications Hub. When relevant, specific documents from this hub will be referenced in the chapters that follow.