CSR Controller
The Control and Status Registers (CSR) Controller is the largest component in DRISC-V. It is responsible for managing system instructions, storing CSRs, and handling interrupts and exceptions. Its implementation is optional, as it does not directly affect the execution of standard instructions.
The CSR Controller includes two interfaces for communication with the Operation Controller and the Program Counter. These interfaces provide essential data for detecting and handling exceptions within the system. The following table summarizes these connections:
| Signal | Connects To | Input/Output | Description |
|---|---|---|---|
| Current Instruction | Operation Controller | Input | Serves as the Trap Value for certain exceptions. Parameters like funct3 are extracted from it. |
| Next Instruction | Operation Controller | Input | Decoded into system instructions and CSR addresses. |
| Next Decoded Instruction | Operation Controller | Input | Used to verify if the next opcode is valid or a system instruction. |
| Load, Store, and Jump | Operation Controller | Input | Triggers misalignment exceptions caused by these instructions. |
| Exception | Operation Controller | Output | Signals that an exception has occurred. |
| Next System Load | Operation Controller | Output | Used to load CSRs mapped in external memory, prompting a load instruction. |
| System Jump | Operation Controller and Program Counter | Output | Signals a jump using the System Target Address. |
| System Load | Program Counter | Output | Signals the PC to use the System Target Address for loading. |
| Calculated Address | Program Counter | Input | Contains the address calculated by the PC for jumps and load/store operations. |
| System Target Address | Program Counter | Output | Contains the address used for system jumps and loads. |
In addition to these connections, the CSR Controller also interfaces with the A and C Buses for CSR manipulation instructions. It receives inputs for the Phase and Interrupt signals as well.
You can see in the image of the component that it contains the value of most CSRs listed in the (Available ISA Page)[./available-instruction-set#machine-level-csrs-and-counters]. Not all are 32 bit, and the reason for that is that not all bits are necessary to be stored, and instead can be hardwired to zero. The CSRs that are not present aren't obtained through registers, and those are the mip, that is obtained through the the interrupt signals inputs, and the time CSR, which is mapped in memory and obtained from an external device.
