-
Notifications
You must be signed in to change notification settings - Fork 0
Home
In this manual, you'll find essential information about the inner workings of the architecture, along with detailed explanations of the various features available in the project.
Below is a summary of the main sections available:
Details the internal structure of the DRISC-V processor, with a breakdown of its components and how they implement the RV32IM Zmmul Zicsr RISC-V specification. Includes a brief overview of available I/O devices.
Presents the graphical simulation models built in Logisim, including instructions on how to run, modify, and experiment with the architecture using a visual interface.
Presents the simulation environment implemented in SystemVerilog, including instructions on how to run, modify, and experiment with the architecture using HDL code.
Describes how to use the custom C# assembler developed for this project, including steps to assemble programs and load them into the simulation environments.
stub: TODO
-
- 1.1 Introduction
- 1.2 RISC-V Implementation
- 1.2.1 Available Instruction Set
- 1.2.2 Available Non-ISA Features
-
- 2.1 ALU
- 2.2 Register File
- 2.3 Program Counter
- 2.4 Input Buffer
- 2.5 RAM
- 2.6 Operation Controller
- 2.7 CSR Controller
-
- 3.1 Input Devices
- 3.1.1 Keyboard
- 3.1.2 Switches and Joystick
- 3.1.3 Random Number Generator
- 3.1.4 Real-Time Device
- 3.2 Output Devices
- 3.2.1 Screen
- 3.2.2 Terminal
- 3.2.3 Software Interrupt Register
- 3.1 Input Devices