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Main Internal Components

Diogo Valadares Reis dos Santos edited this page Aug 16, 2025 · 7 revisions

Introduction

The DRISC-V architecture is composed of six internal components: the ALU, the Register File, the Program Counter, the Input Buffer, the Operation Controller, and the CSR Controller.

The DRISC-V architecture comprises six internal components: the ALU, the Register File, the Program Counter, the Input Buffer, the Operation Controller, and the CSR Controller.

These components communicate through five internal buses. The A, B, and C buses provide direct access to the Register File (A and B are used for reading register values, while C is used for writing results back). The Immediate Bus supplies the 32-bit immediate value extracted from the current instruction. Lastly, the Program Counter Bus carries the current instruction address from the Program Counter.

There are also two buses used for external communication: the IO Bus, used for data transfers, and the Address Bus, which provides the current address being used. The IO Bus connects with the B bus and the Input Buffer. The current address can indicate either the address of the current instruction or the address used in load and store instructions.

The following tabe gives a summary of all the busses and which components they are connected to.

Bus Connections Overview

Bus Name Sources Destinations
A Bus Register File ALU, Program Counter, Operation Controller, CSR Controller
B Bus Register File ALU, IO Bus
C Bus ALU, Input Buffer, Program Counter, Immediate Bus, CSR Controller Register File
Immediate Bus Operation Controller ALU, C Bus
Program Counter Bus Program Counter ALU, CSR Controller
IO Bus External Devices, B Bus External Devices, Operation Controller, Input Buffer
Address Bus Program Counter External Devices

The following image shows a simplified diagram of all internal components, along with their bus connections.

Note: There are short buses connecting the CSR Controller to both the Operation Controller and the Program Counter. These have been omitted from the diagram as they are highly specialized and not part of the general data flow.

DRISC-V Internal Architecture Diagram

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