Running the Simulation
This guide covers the basics of using Logisim Evolution. For a more detailed overview of available features, refer to the embedded documentation found in the Help menu, available in multiple languages.
After opening the project file as described on the previous page, you should see the full DRISC-V circuit. If not, try zooming out or click the Auto button in the lower-left corner of the window.
To start the simulation, switch from the Design tab to the Simulate tab. This will reveal the simulation control buttons.
These buttons control the simulation execution. You can hover over each one to see its function. Typically, you'll only need two:
- The first button: starts and stops the simulation.
- The third button: pauses clock cycles but allows signals to propagate.
Activating both will start the simulation. However, it won’t do anything initially, since the memory is filled with garbage data rather than a valid program.
To run a program, locate the RAM component(it's the first component on the right side of the circuit). Right-click on it and select Load Image:
All available programs are located in the DRISC Programs folder at the root of the project and use the .mem extension. Before loading remember to pause the simulation or the clock cycles to avoid overwriting RAM data.
After loading a program, it’s recommended to reset the simulation, as some registers may retain old values that could interfere with execution. You can reset by pressing CTRL+R or navigating to Simulate > Reset Simulation.
Once reset, the simulation should begin executing the loaded program.
If the simulation crashes, you don’t need to restart Logisim. Instead:
- Reset the simulation.
- Click the play button to resume animation.
- Re-enable clock cycles if they were disabled.
To inspect the internal circuit of any component:
- Use the Design List on the left.
- Select the Poke Tool (hand icon) and double-click the component.
- Or, right-click the component and choose View Component.
With the verilog folder opened in Visual Studio Code, begin by opening the DRISC testbench file named test_drisc.sv. At the top of this file, you'll find several important parameters that control the simulation.
In most cases, you'll only need to modify the RAM_DATA parameter, which points to the program file that will be executed during the simulation. Occasionally, the PROGRAM_SIZE may be too large or too small. If that happens, the simulation will usually display a warning, and you can simply adjust the value accordingly.
Other useful parameters include:
-
INSTRUCTION_COUNT: Limits how many instructions will run before the simulation stops automatically -
CSR_ENABLE: Enables the generation of the CSR Controller -
DISPLAY_TOGGLE: Controls how simulation output is displayed in the terminal-
0: Shows register and bus values at every clock cycle -
1: Updates less frequently and displays fewer registers -
2: Displays each instruction in a mathematical format (recommended for general use)
-
Once you've set RAM_DATA to the desired program, start the simulation by opening the PowerShell terminal in VS Code and running:
./RunSimulation.ps1If you're not on Windows, you can run the command directly from the script:
iverilog -Wall -g2012 -s test_drisc test_drisc.sv | vvp a.outThe simulation will run continuously until it enters an infinite loop or reaches the instruction count limit. To stop it manually, press CTRL+C in the terminal.
If the simulation ends normally (without CTRL+C), the contents of the Register File will be printed, showing each register's name, hexadecimal value, and signed decimal value. This is followed by the contents of RAM, displayed in both hexadecimal and ASCII formats. Modified data is highlighted in red, as shown in the result of the quicksort algorithm below:
Since the simulation runs in the terminal, it doesn't support the same user I/O features as Logisim. To bridge this gap, a companion program was created to provide a similar interface. You can find it at:
verilog/interface/SystemVerilogIntegration.exe
After launching the program, you'll be able to view screen and terminal output from the simulation and type input using the keyboard interface.
As mentioned on the First Steps page, this executable requires the .NET Framework. If you prefer not to install it, you can download a version with the embedded framework from the releases page of this repository.