Software Interrupt Register

The Software Interrupt Register

The Software Interrupt Register, similar to the Real-Time Device, is a memory-mapped CSR component. In this case, it serves as an interrupt signal for the mip CSR. This register allows software and other harts (processor cores) to trigger an interrupt by writing to it. It is implemented as a simple register connected to a single byte of memory.

It can only be written to and cannot be read directly. To read its value, you must access it through the mip CSR.

SystemVerilog Code

wire is_software_interrupt_address = (address_bus == 32'h81000014);
assign software_interrupt = software_interrupt_reg;

reg software_interrupt_reg;

always @(posedge clock) begin
    if (reset)
        software_interrupt_reg <= 0;
    else if (write && is_software_interrupt_address)
        software_interrupt_reg <= data_bus[0];
end