Terminal
The Terminal is a component that allows text to be displayed by the machine without the need to render each character pixel-by-pixel, making it ideal for displaying system messages.
The terminal interface is much simpler than the screen. It requires only a 7-bit ASCII input, a clock signal, and a clear-terminal signal.
To write to the terminal in a program, use a store byte (sb) instruction. Since the terminal includes an internal buffer, only one address is needed for writing data. To clear the terminal, send a write signal to the next address using another sb instruction.
In the SystemVerilog simulation interface, the terminal is located on the right side of the window:
In the SystemVerilog code, the terminal operates using a shift register. When new data is written to the first register, the existing contents are shifted down the buffer. When writing to the external file, the entire buffer is saved in a hexadecimal, byte-separated format.
`timescale 1s/1s
module terminal #(
parameter string TERMINAL_FILE = "terminal.mem"
)
//inputs and outputs
(
input logic clock,
input logic reset, // Added reset signal
input logic write,
input logic [7:0] data
);
//shift register
logic [7:0] buffer [0:63];
always @(negedge clock) begin
integer file_handle;
//reset logic
if (reset) begin
for (int i = 0; i < 64; i++) begin
buffer[i] <= 8'd0;
end
file_handle = $fopen(TERMINAL_FILE, "w");
if (file_handle != 0) begin
$fclose(file_handle);
end
end
//write logic
else if (write) begin
//this generates a shift register
for (int i = 63; i > 0; i--) begin
buffer[i] <= buffer[i-1];
end
buffer[0] <= data;
// Clear the file before writing new buffer contents
file_handle = $fopen(TERMINAL_FILE, "w");
if (file_handle) begin
foreach (buffer[i]) begin
$fdisplay(file_handle, "%h", buffer[i]);
end
$fclose(file_handle);
end
end
end
endmodule