feat(rcu): add persistent CPU context tracking - #2218
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fslongjin merged 2 commits intoAug 29, 2026
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Introduce a cacheline-aligned per-CPU context state machine for kernel, user, idle, IRQ, and NMI contexts. Track quiescent-state generations so grace periods can exclude CPUs already in extended quiescent states and credit CPUs that pass through one after a grace period starts. Wire the context boundaries into x86_64 and RISC-V entry, interrupt, idle, and user-return paths. Keep architecture code limited to paired transition hooks, preserve nested interrupt semantics with typed tokens, and retain the grace-period waiting mask as the source of truth. Add deterministic transition and grace-period selftests, debug-only misuse diagnostics, and a dedicated RCU architecture document covering the stable context, grace-period, callback, ordering, and integration principles. Validated with make fmt, make kernel, a RISC-V kernel link, and two consecutive 2/2 RCU dunitest passes in a two-vCPU x86_64 QEMU guest. Closes DragonOS-Community#2210 Signed-off-by: longjin <longjin@dragonos.org>
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Add the English RCU chapter and architecture guide alongside the Chinese source documentation. Preserve the same subsystem structure, context model, grace-period proofs, callback lifecycle, integration principles, and design boundaries in both language trees. Link the new chapter from the English kernel documentation index and keep all diagrams and section ordering aligned with the source document. Signed-off-by: longjin <longjin@dragonos.org>
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Summary
Design
The context tracker owns only per-CPU state transitions and quiescent-state generations. The grace-period state owns participant snapshots and the waiting mask, while the coordinator is the only layer that combines online CPU state, context snapshots, and callback progress. Architecture code only reports real entry and exit boundaries and does not maintain a second copy of RCU state.
The common transition path remains per-CPU and allocation-free. A per-CPU report hint prevents CPUs already credited for the active grace period from repeatedly taking the global slow path. The grace-period waiting mask remains the correctness source of truth.
User and idle contexts are persistent extended quiescent states. IRQ and NMI nesting temporarily restore RCU watching and only the outermost exit may restore the interrupted base context. Typed, single-use tokens make idle and IRQ entry and exit pairing explicit.
Correctness
Grace-period start and context transitions use an ordered two-way handshake. A CPU that enters an extended quiescent state before the snapshot is observed directly; a CPU that transitions after being recorded advances its generation and reports progress. A post-snapshot recheck closes the overlap window.
The x86_64 exception entry keeps the original error code in the completed trap frame across the Rust entry helper and reconstructs the handler ABI afterwards, preserving volatile-register semantics. User-accessible overflow and bounds gates use interrupt-gate entry so the context helper cannot be interrupted before the kernel state is established.
Validation
Closes #2210