ESP32JTAG Firmware v0.2.1

ESP32JTAG Firmware v0.2.1

ESP32JTAG v0.2.1 is a maintenance release based on v0.2.0.

Fixed

• Improved Logic Analyzer rendering and hover-measurement scheduling to prevent
  high CPU usage and apparent browser freezes during waveform interaction.
• Restored saved Logic Analyzer trigger indicators correctly after a browser
  refresh, together with the existing sample-rate, measurement, and internal
  signal settings.
• Corrected Logic Analyzer time and frequency measurements below 33 MHz. The
  former 0.26M and 0.5M choices could not be generated by the FPGA; the Web UI
  now exposes the actual minimum rate of 0.518M samples/s.
• Ensured active-LOW SReset returns to its inactive level during startup and
  restart instead of holding the target MCU in reset.
• Connected Black Magic GDB hardware-reset commands to the ESP32JTAG SReset
  output.

Compatibility

• Hardware: ESP32JTAG V1.40
• Build environment: ESP-IDF v5.5.2
• OTA upgrades from v0.2.0 preserve existing NVS configuration.
• The lowest Logic Analyzer setting is now labelled 0.518M; legacy API
  requests for 0.26M or 0.5M are accepted and report the effective 0.518M rate.

Install

• Use the _ota.bin image from the dashboard's Firmware Update tab for a
  normal upgrade.
• Use the _full.bin image at flash offset 0x0 for factory programming or
  recovery.

Back up any important configuration before an upgrade. Do not interrupt power
while an OTA or full-flash operation is in progress.