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I did, but my goal here is not to optimize dma buffer by splitting read and write, but simply fixing a wrong alignment we are using today. Your link actually highlight the need for this change: "Please note that in case of reception there can be problem if rx_buffer is not aligned to the size of cache-line (32-bytes), because during the invalidate operation another data sharing the same cache-line(s) with rx_buffer can be lost." |
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This was also in #6484 so not merging. |
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Align DMA buffers to 32bytes on H7
Fixes #6509
Thanks Radiomaster for spotting that one.