Data Sheet

Introduction

This project involves redesigning the 74181 4-bit ALU at the functional level as part of the Verilog learning process. The logic circuits were constructed according to each function, and the transistor-level circuit was implemented using Logisim simulation.

The newly designed ALU provides the same functions as the 74181 ALU but differs in the function arrangement based on the selection signals defined in the datasheet. A new arrangement was designed with optimization at both the logic and transistor levels in mind.

Circuit

Input

S : Selection - 4 bit

M : Mode - 1 bit

A : Number A - 4 bit

B : Number B - 4 bit

C_in : Carry In - 1 bit

S (Selection, 4-bit)

• A 4-bit selection signal that determines which operation to perform.
• It ranges from 0000 to 1111 (16 different operations).
• If M=1, logical operations are performed.
• If M=0, arithmetic operations are performed.

M (Mode, 1-bit)

• A mode selection signal.
• M=1 → Logical operation mode.
• M=0 → Arithmetic operation mode.

A (Number A, 4-bit)

• A 4-bit operand.
• Used as a primary input in most operations.

B (Number B, 4-bit)

• A 4-bit operand.
• Used as a secondary input in some operations.

C_in (Carry In, 1-bit)

• A carry-in signal.
• Only affects arithmetic operations (M=0).
• If C_in=0, normal addition/subtraction is performed.
• If C_in=1, operations consider an initial carry.

Output

F : Output Number - 4 bit

same : Same Flag - 1 bit

C_out : Carry Out - 1 bit

GG : Group G - 1 bit (CLA)

GP : Group P - 1 bit (CLA)

F (Output Number, 4-bit)

• The final result of the operation.
• It stores the result of either a logical or an arithmetic operation.

same (Same Flag, 1-bit)

• Indicates whether A and B are equal.
• same = 1 → A and B are the same.
• same = 0 → A and B are different.

C_out (Carry Out, 1-bit)

• Represents the carry-out (or borrow in subtraction) from an arithmetic operation.
• Only meaningful when M=0 (arithmetic mode).
• It signals an overflow from addition or a borrow from subtraction.

GG (Group Generate, 1-bit, CLA)

• A signal used in the Carry Lookahead Adder (CLA) to indicate group carry generation.
• GG = 1 → A carry is always generated within the group.
• GG = 0 → No carry is generated in the group.

GP (Group Propagate, 1-bit, CLA)

• A signal used in the CLA to indicate group carry propagation.
• GP = 1 → The group may propagate a carry from the previous stage.
• GP = 0 → The group does not propagate a carry.

Logical Operation

S	M	Logic
0000	1	0000
0001	1	~(A|B)
0010	1	(~A)&B
0011	1	~A
0100	1	A&(~B)
0101	1	~B
0110	1	A^B
0111	1	~(A&B)
1000	1	A&B
1001	1	~(A^B)
1010	1	B
1011	1	(~A)|B
1100	1	A
1101	1	A|(~B)
1110	1	A|B
1111	1	1111

Arithmetic Operation C == 0

S	M	C	N1	N2	Arithmetic
0000	0	0	A	A	2 A
0001	0	0	A	A|~B	A + A|~B
0010	0	0	A	A|B	A + A|B
0011	0	0	A	1111	A - 1
0100	0	0	A&B	A	A&B + A
0101	0	0	A&B	A|~B	A&B + A|~B
0110	0	0	A	B	A + B
0111	0	0	A&B	1111	A&B - 1
1000	0	0	A&~B	A	A&~B + A
1001	0	0	A	~B	A - B - 1
1010	0	0	A&~B	A|B	A&~B + A|B
1011	0	0	A&~B	1111	A&~B - 1
1100	0	0	0000	A	A
1101	0	0	0000	A|~B	A|~B
1110	0	0	0000	A|B	A|B
1111	0	0	0000	1111	-1

Arithmetic Operation C == 1

S	M	C	N1	N2	Arithmetic
0000	0	1	A	A	2 A + 1
0001	0	1	A	A|~B	A + A|~B + 1
0010	0	1	A	A|B	A + A|B + 1
0011	0	1	A	1111	A
0100	0	1	A&B	A	A&B + A + 1
0101	0	1	A&B	A|~B	A&B + A|~B +1
0110	0	1	A	B	A + B + 1
0111	0	1	A&B	1111	A&B
1000	0	1	A&~B	A	A&~B + A + 1
1001	0	1	A	~B	A - B
1010	0	1	A&~B	A|B	A&~B + A|B + 1
1011	0	1	A&~B	1111	A&~B
1100	0	1	0000	A	A + 1
1101	0	1	0000	A|~B	A|~B + 1
1110	0	1	0000	A|B	A|B + 1
1111	0	1	0000	1111	0